Why is I2S Frequency in Clock Configuration so high?

[Stipe]

Hi STM community!

I am new to STM microcontrollers and this is my first post :)

My board is a tiny STM42F401CCU6 @ 84MHz. I already have made some first steps with CubeMX and CubeIDE, after I came from the arduino IDE which was a bit too simple (reading some ADC voltages, driving a 7-Segment Display with a shift register).

Some day I want connect a HIFI DAC (PCM5102) to I2S in order to build a VA synthesizer, using a Half Duplex DMA Transfer. This is a challange for me, because there are so many things to configure in the CubeMX. The programming itself seems quite smooth thanks to the CubeIDE and CMSIS.

My current focus is the clock configuration, which is quite complex stuff for MC beginners. I have watched some YouTube vids from STM but I wondered, why the I2S clock ist so high, when I configure a I2S interface. At any sample rates it is set to 96MHz, even when the HCLK is only 16MHz.

I thought, the I2S clock is calculated by sampleRate*BitsPerSample*Channels, which is only 128kHz on 8kHz 16 Bit Sound. The minimum i2s multiplier is x50, in the screenshot you see my default configuration...

Can somebody explain or give some advice or sources on that clock Issue?

Cheers, Stipe

[TDK · Accepted solution]

There's no issue here. What you are seeing is the kernel clock rate for the peripheral. It's not the data speed. The data speed will be much less according to the setup of the peripheral in the I2C tab. The data speed will typically be 100 or 400 kHz, but the kernel clock needs to be much higher so it can subsample appropriately.

16 MHz / 16 * 192 / 2 = 96 MHz.