@FBL Is it correct that so many registers (see image, marked as yellow) has been cleared after execution of
/* Core Soft Reset */
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; ?
Currently, my source code looks like:
void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
{
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(pcdHandle->Instance==USB1_OTG_HS)
{
/* USER CODE BEGIN USB1_OTG_HS_MspInit 0 */
/* USER CODE END USB1_OTG_HS_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBOTGHS1;
PeriphClkInitStruct.UsbOtgHs1ClockSelection = RCC_USBOTGHS1CLKSOURCE_HSE_DIRECT_DIV2;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Enable VDDUSB */
HAL_PWREx_EnableVddUSB();
/* USB1_OTG_HS clock enable */
__HAL_RCC_USB1_OTG_HS_CLK_ENABLE(); // RCC->AHB5ENSR
__HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE(); // RCC->AHB5ENSR
/* USB1_OTG_HS interrupt Init */
HAL_NVIC_SetPriority(USB1_OTG_HS_IRQn, 7, 0);
HAL_NVIC_EnableIRQ(USB1_OTG_HS_IRQn);
/* USER CODE BEGIN USB1_OTG_HS_MspInit 1 */
/* Reset USB peripherals and configure the HSE clock */
RESET_USB_MACRO();
HAL_Delay(10);
USB1_HS_PHYC->USBPHYC_CR = 0x10025; // 1: The VBUS valid comparator is powered down. The session valid comparator is ON (default)
// 010: 24 MHz
// 1: PHY clocks are off during Suspend and Sleep mode. PLL is off.
// 1: Retention mode disabled (default)
__HAL_RCC_USB1_OTG_HS_PHY_RELEASE_RESET();
/* Required few clock cycles before Releasing Reset */
HAL_Delay(10);
__HAL_RCC_USB1_OTG_HS_RELEASE_RESET();
/* USER CODE END USB1_OTG_HS_MspInit 1 */
}
}
