Appreciate your quick and always valuable answers and feedback.
Descriptor based cyclic multibuffer use is quite a common scenario in high speed data captures be it audio, video etc. I use it all the time in many DSP and FPGA architectures (with ARM SoC etc). It frees the cpu from reprogramming the DMA after each cycle to avoid over writing the buffers by switching to another buffer automatically at the end of a cycle.
In many architectures it is implemented as Scatter-Gather DMA with several flexible features to perform these complex and varied data capture operations with no cpu interventions at all, all via pre-programed DMA descriptors.
But in STM32 DMAs, there's no descriptor feature supported and this alternate multibuffer scheme (actually it's only a double-buffer) helps somewhat by enabling the use of a ping-pong buffer scheme which is ok for such uses with proper programming design.
I use the DFSDM block which is a very useful block for advanced audio captures from PDM microphones with custom sampling rates, resolutions, multiplexing etc possible compared to other schemes. But all these are useful only if such a multibuffer DMA is used. In the sample applications provided by ST Micro, a simple very inefficient dma scheme is used where one needs to use cpu to copy half the buffers by enabling the Half-Buffer Complete DMA interrupts. It's ok for simple, low-speed applications but not for high-speed, complex applications. (in fact in my use it miserabley fails when I increase the data rates.
Anyway, I'll have figure out using the best way to implement this scheme by directly controlling the DFSDM block and the DMA controller etc.
Again, thanks for your inputs..best regards
