STM32CubeMX 6.16.1 - STM32H7 ADC3 clock/prescaler migration issue

[gsilva_bretgeld_eng]

I have an ST32CubeMX project for a STM32H7 mcu generated with STCubeMX 6.4 and using STM32Cube FW_H7 V1.9.1 where the project files are generated via cmake. Now I want to use STM32Cube FW_H7 V1.12.1, but apparently, in order to be able to generate the new files, I have to migrate the project to STM32CubeMX 6.16.1:

The problem is that, once I click in "Migrate", it removes two important lines from my code:



So, I went to CubeMX to check, and apparently, at a first glance, the field to configure ADC3 Prescaler is gone ( I do not have any other ADC on):


Also, the clock configuration tab was showing a problem. I went to check and apparently ADC clock is not allowed to be more than 100 MHz anymore:

Unfortunately, I can not slow PLL2P down, since it is used for other peripherals (e.g. SPI), but I could maybe change the clock source to PER_CK and then derive it from HSI to have it as 25 MHz ( 150 MHz + Prescaler of 6 ), although I do not know which other implications it could have.

I looked up some Issue and Release notes but I could not find anything about that. Is that an already known issue?

[Mahmoud Ben Romdhane]

Hello @gsilva_bretgeld_eng 

Let me thank you for posting.

For more investigation, I suggest that you provide your Ioc.File.

Thanks.

Mahmoud

[gsilva_bretgeld_eng]

Hello Mahmoud, thank you for your reply. I think I am not allowed to share my ioc here, but I am using a STM32CubeMx 1.16.1, STM32Cube FW_H7 V1.21.1 and a STM32H743ZITx microcontroller. My main problem is that the ADC3 does not have the field to configure the prescaler anymore, neither I can configure a 150 MHz clock in the ADC Select Mux. This happened after I migrated my project from CubeMX 6.4.

Thanks.

Gabriel

[Mahmoud Ben Romdhane]

Hello @gsilva_bretgeld_eng 

Let me thank you for bringing this issue to our attention.

The issue has been escalated internally to the dedicated team for further investigation and resolution (Ticket 227116).

As WA, I recommend that you add the code manually: hadc3.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV6;

I will let you know when the issue is fixed.

For the ADC Clock frequency, I suggest that you take a look at DS12110 Rev 11 Table 174. ADC characteristics (1).

Thanks.

Mahmoud

[gsilva_bretgeld_eng]

Hello @Mahmoud Ben Romdhane

Thank you for bringing my attention to that, it is true, there is an "USER CODE" area right before the configuration of the ADC where I can do that. Regarding the clock, I assume that F_adc is the final ADC Clock, since the highest clock presented is at least half of the clock that is now allowed by the ADC Mux in the clock tool. Also, in my project, with 150 MHz from ADC Mux plus a /6 prescaler (not counting if it is revision V or Z) the ADC Clock should be 25MHz, which is completely suitable according to the datasheet. I am assuming here that F_adc is the final frequency of Figures 136 and 137 from RM0433 Rev 6. Of course, I can do some workarounds on that as well, but I was just wondering why in the STM32CubeMX 6.4 the limit was 160 MHz and now it is just 100 MHz, because the size of the prescaler depends on that.

Thanks once again,

Gabriel

[Mahmoud Ben Romdhane]

Hello @gsilva_bretgeld_eng 

Issue is fixed in the latest STM32CubeMX release 6.17.0.

You can get it through this link.

Thanks

Mahmoud

[gsilva_bretgeld_eng]

Hello @Mahmoud Ben Romdhane 

Thank you, the missing field in ADC configuration is indeed back, but the code generation still deletes this line from my project and does not generate a new one:

Also, I still can not set the ADC Clock as 150 MHz as it was before, just until 100 MHz:

The previous limit was 160MHz as it can be seen below:
 
Is it an error from the new version or was it an error before that was corrected now?

thank you once again,

Gabriel

[Mahmoud Ben Romdhane · Accepted solution]

Hello @gsilva_bretgeld_eng 

Further to your last comment, I confirm that the clock prescaler code line is not generated on static void MX_ADC3_Init(void).

The issue has been submitted to the dedicated team under this internal ticket (Ticket Number: 227955)

You can notice through the Reference Manual, Table 60. Kernel clock distribution overview, that the Maximum allowed ADC Frequency is 100 MHz for Power Regulator Voltage Scale 0 or 1 and 80 MHz for Power Regulator Voltage Scale 2 or 3.

I will be waiting for your feedback.

Thanks.

Mahmoud

[gsilva_bretgeld_eng]

Hello @Mahmoud Ben Romdhane 

I see, you are right, so it was a previous mistake that was fixed in the newer versions. I will adjust that on my projects and then wait until the MX_ADC3_Init is fixed. Should I mark "Accept as Solution" then?

Thanks again, 

Gabriel