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STM32CubeMX 6.10.0 limit source frequency for ADC

Associate II

I am trying to configure ADC for STM32H562VGT in STM32CubeMX but it is limiting maximum source frequency for ADC. It limits it to 75MHz (which is maximum frequency of ADC clock) but ADC clock has its internal divider.

For example I want to use 120MHz HCLK as a source for ADC clock and set internal divider to 64 but Cube is notifying me with Clock issues.

In version 6.8.0 this problem was not present and I could use 120MHz clock as clock source for ADC.

Is it some bug in new version of Cube?




the max clock depends on core voltage setting - cube shows/limits according to this setting.



set to scale0 for max frequencies. .... and max power consumption. 🙂

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ST Employee

Hello @BlazejKrysztofiak 

First let me thank you for posting!

As per DS14258  it is mentioned that the maximum source frequency for ADC is 75Mhz.

This fix was added in the last version 6.10 to ensure that CubeMX will be aligned with the Datasheet.


Thank you!


@Souhaib MAZHOUD I thought that this restriction applies directly to ADC clock (3) no to clock from which ADC clock is derived (1 or 2) because 1 or 2 can be further divided to achieve lower frequency of ADC and as for now Cube doesn't let me set 2 frequency higher than 75MHz no matter what divider I set for ADC clock.

Also this restriction can be still omitted by using 1 as clock source because we can set hclk to frequency higher than 75MHz and we can use divider set to 1 and Cube lets us do it.



Thank you for answering but in my case it doesn't make difference.

right. (i tried on my H563 nucleo board now).

i think, Cube is wrong here, on V 6.9.1 (i use here) , allowing 125MHz for ADC. (250M /2 setting).

and your V 6.10. also wrong... 🙂

for my understanding the ADC can work with max. 75MHz, (pos. 3 in your pic from rm);

and input clk (pos. 1 or 2 ) can be divided down to meet this.

so @Souhaib MAZHOUD  is also wrong, because 75M is just the max clk for ADC, not for input to the ADC prescaler. He says same as Cube V 6.10. : limit the adc_ker_clk to 75M, but it should just limit the ADC_clk to 75M by setting the prescaler correct.

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