I am attempting to use CubeMX to generate the code necessary to do a very basic demo of TX DMA using the LPUART and the BDMA peripheral (which as I understand it handles DMA for the LPUART1 which I'm using).
Based on my reading of the reference manual, I'm supposed to enable the DMA TX channel under the LPUART DMA tab. I am assuming I can choose any of the BDMA "channels" (which I assume are the new version of DMA Streams in older STM32 MCUs); I picked BDMA Channel 0, and checked the "Enable Event" and used Event Request 10 (per Reference Manual RM0468 Table 121, Page 678). I also enabled the LPUART1 Global Interrupt, BDMA Channel 0 Global Interrupt and the DMAMUX2 overrun interrupt. However, if I generate the project using these settings and attempt to use the HAL_UART_Transmit_DMA() function to send a sample string, I get nothing as output. I am still able to use the polling calls to send data.
Is there anything additional the user is expected to do to make this work? I'm tearing my hair out trying to get a simple DMA transmit to work, and it appears documentation on this is extremely sparse (or at least, scattered in a million different areas.) I've also tried just letting CubeMX generate the startup code and then poked directly at the LPUART+BDMA+DMAMUX2 registers as follows:
uint8_t buf[] __attribute__ ((aligned(4),section("RAM_D3"))) = "hello\r\n";
void dma_test(void)
{
__disable_irq(); // Don't need interrupts for fixed-length DMA TX for now...
LPUART1->CR3 |= 1<<7; // Set DMAT bit to enable DMA TX Req at LPUART IP end
__HAL_RCC_BDMA_CLK_ENABLE(); // Ensure BDMA Clock enabled. Q: Does DMAMUX have its own RCC bit somewhere? Didn't spot it spelunking in the H730 header...
BDMA_Channel0->CCR &= ~(1<<0); // Clear EN bit to allow BDMA transfer setup
BDMA_Channel0->CPAR = LPUART1_BASE+0x28; // Periph addr = LPUART TDR
BDMA_Channel0->CM0AR = &buf[0]; // Mem addr = beginning of TX buffer in SRAM D3 region
BDMA_Channel0->CNDTR = 7; // 7 byte transfer, using default MSIZE of 1 byte
BDMA_Channel0->CCR = 1<<7 | 1<<4; // DIR, MINC=1
DMAMUX2_Channel0->CCR = 1<<9 | 10<<0; // Enable Event, Event 10
LPUART1->ICR = 1<<6; // Clear TCCF per LPUART DMA TX setup procedure, RM0468, Para 54.4.12, Page 2168
SCB_CleanInvalidateDCache();
BDMA_Channel0->CCR |= 1<<0; // Enable DMA Transfer
}
Any advice would be much-appreciated!
