CubeMX 6.16.1
MacOS 15.7.3
STM32F469NIHX
Multimedia - DSIHOST - Data and Clock Lanes - click,click,click
Show Advanced Parameters - check
HS Transmission fine tuning and LP Transmission fine tuning
Transmission Delay on Clock Lane and Transmission Delay on Data Lanes
These items refer to 2-bit wide fields in DSI_WPCR1 but CubeMX allows values from 0-10, which would be 3.32-bits wide. By setting the clock transmission delay to, say, 10, the data clock delay gets overwritten as well. Data delay overwrites the low power clock delay, and so on.
The actual data range for these items should be [0,3], and HAL_DSI_SetSlewRateAndDelayTuning should probably sanitize the parameter Value before using it.
