Hi all, I'm new to this STM32 community.
I have a small problem: I bought some STM32G0P0.. for my project, also making the PCB and the rest. But after soldering the various components, I try to program one and see that the level 2 protection is active, I try to program another and there is the same thing.
What I see from the STM32 St-LINK program is that only some memory pages have protection, while others don't, but then going to view the memory areas I see that they have all been set to FFFFFFFF.
Below I can see that the memory on the address 0x08001400 is free, but..
..here I see that is protected! How can I program it?
My question now is: what the hell do I do? Do I ask for a return? Is this a normal thing of STM32G0...? Trying to write a bootloader that makes me jump from one address to another when the memory to read is full?
Thank you for your availability and attention
Hi @mattias norlander . For your previous answer: thank you and yes, everything you said is correct.
Now I tried to change the resistors that were located between the pins of the microcontroller and the connectors to which SWDIO and SWCLK of the ST-LINK/V2 are connected, and debugging goes with many problems (I remember that before changing the resistors the debugging).
Now that I've changed the resistors, from 1k to 20ohm, I can debug (SWD, Connect Under Rest or Software System Reset, 950khz), but the errors I get are these:
and
Open On-Chip Debugger 0.11.0+dev-00449-g53fa0f7 (2022-06-09-09:42) [https://github.com/STMicroelectronics/OpenOCD]
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : STLINK V2J40S7 (API v2) VID:PID 0483:3748
Info : Target voltage: 3.208388
Info : clock speed 950 kHz
Info : stlink_dap_op_connect(connect)
Info : SWD DPIDR 0x0bc11477
Info : STM32G050F6Px.cpu: Cortex-M0+ r0p1 processor detected
Info : STM32G050F6Px.cpu: target has 4 breakpoints, 2 watchpoints
Info : STM32G050F6Px.cpu: external reset detected
Info : starting gdb server for STM32G050F6Px.cpu on 3333
Info : Listening on port 3333 for gdb connections
Info : accepting 'gdb' connection on tcp/3333
target halted due to debug-request, current mode: Thread
xPSR: 0xf1000000 pc: 0x1fff1654 msp: 0x20000e48
Info : device idcode = 0x10006456 (STM32G05/G06xx - Rev A : 0x1000)
Info : RDP level 0 (0xAA)
Info : flash size = 32kbytes
Info : flash mode : single-bank
Error: Failed to read memory at 0xfffffffe
Error: Failed to read memory at 0xfffffffe
Info : accepting 'gdb' connection on tcp/3333
target halted due to debug-request, current mode: Thread
xPSR: 0xf1000000 pc: 0x1fff1654 msp: 0x20000e48
Info : Padding image section 0 at 0x080018c4 with 4 bytes (bank write end alignment)
target halted due to debug-request, current mode: Thread
xPSR: 0xf1000000 pc: 0x1fff1654 msp: 0x20000e48
Info : STM32G050F6Px.cpu: external reset detectedThanks for your help and availability
Hi @mattias norlander if it can be useful, here is the wiring diagram of how I did the programming part of the MCU:
Since I changed those two 1k resistors of SWDIO and SWDCLK (R14 - R15) I get the error from the previous post.
Did I miss something in the wiring diagram?
Thanks again for everything and happy holidays to all
Hi @Piranha , I removed R17 and instead of R18 I put a wire to make C1 directly connected to the NRST.
Once this is done... nothing has changed:
and
Open On-Chip Debugger 0.11.0+dev-00449-g53fa0f7 (2022-06-09-09:42) [https://github.com/STMicroelectronics/OpenOCD]
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : STLINK V2J40S7 (API v2) VID:PID 0483:3748
Info : Target voltage: 3.215717
Info : clock speed 950 kHz
Info : stlink_dap_op_connect(connect)
Info : SWD DPIDR 0x0bc11477
Info : STM32G050F6Px.cpu: Cortex-M0+ r0p1 processor detected
Info : STM32G050F6Px.cpu: target has 4 breakpoints, 2 watchpoints
Info : STM32G050F6Px.cpu: external reset detected
Info : starting gdb server for STM32G050F6Px.cpu on 3333
Info : Listening on port 3333 for gdb connections
Info : accepting 'gdb' connection on tcp/3333
target halted due to debug-request, current mode: Thread
xPSR: 0xf1000000 pc: 0x1fff1654 msp: 0x20000e48
Info : device idcode = 0x10006456 (STM32G05/G06xx - Rev A : 0x1000)
Info : RDP level 0 (0xAA)
Info : flash size = 32kbytes
Info : flash mode : single-bank
Error: Failed to read memory at 0xfffffffe
Error: Failed to read memory at 0xfffffffe
Info : accepting 'gdb' connection on tcp/3333
target halted due to debug-request, current mode: Thread
xPSR: 0xf1000000 pc: 0x1fff1654 msp: 0x20000e48
target halted due to debug-request, current mode: Thread
xPSR: 0xf1000000 pc: 0x1fff1654 msp: 0x20000e48
Info : STM32G050F6Px.cpu: external reset detectedIf it can be useful, here is the code of the file startup_stm32g0... that I never touched:
.syntax unified
.cpu cortex-m0plus
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application s entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M0. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window WatchDog */
.word 0 /* reserved */
.word RTC_TAMP_IRQHandler /* RTC through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
.word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
.word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
.word 0 /* reserved */
other configurations
you still start booloader...
please show actual option bytes: (this was your setting)
