Read While Write in STM32U5A9J-DK

[Sanath]

Hi Team,

We are working on STM32U5A9J-DK for one of our application interfaced with Octal SPI Flash.We needed to acheive RWW operation which is supported by our Flash chip and we have used OSPI1 and OSPI2 in multiplexed mode but we are controlling Chip select in software because of the limitation in STM32U5A9 chip and we were able to see Parallel operation of Write and Read which is RWW but an issue is we are unable to read the Bank stat register from the flash chip which gives information of the Bank number which is being Written while Read is happening. Now our doubt is it because of chip select controlled in software its not able to read volatile register properly?

Any input on this?

Sanath

[SofLit]

Hello @Sanath,

This thread has nothing to do do with CubeIDE as your question is related to the product usage. I moved it from STM32CubeIDE forum to STM32 MCU products.

[adamfinch]

As per my knowledge, it is possible that controlling the Chip Select in software may result in some timing issues, especially when attempting to read the volatile Bank Status register.

CS should be managed through software, as the synchronization between read and write operations could be disrupted. It can also prevent accurate reading of the register.

I have read about this one at somewhere at one of the tech based platform.

[Sanath]

Hi @adamfinch 

Below are the steps for performing an RWW (Read-While-Write) operation and the corresponding observations regarding the Bank Stat Register:

1. We initiate the RWW write command for a specific bank.
2. Without terminating the write task, we send the RWW read command to read another bank.
3. Prior to reading, we send the Read Volatile Instruction along with the Bank Stat Register address to check which bank the write operation is targeting.
4. Every time we read the Bank Stat Register; we observe a value of 3 (0x03).
5. When we omit the RWW write command and only send the RWW read command, the value read from the Bank Stat Register is 248 (0xF8), with the 3 least significant bits set to 0. This indicates that no RWW write operation is occurring.

So above steps says that its reading wrong value.

So, all these are being done using Chip select controlled in software. 

Regards,

Sanath

[adamfinch]

Got it know now! Thanks again