Goal: Use PLL functionality on either the HSI or HSE to increase clock speed.
Problem: PLLRDY flag never sets. Enters hard fault and requires reset.
Setup:
IDE: STM32CubeIDE
MCU: STM32F070CB
HSE: NX3225SA-12.000M-STD-CSR-1 loaded with 8pF caps.
Programmer: Chinesium J-link, chinesium ST-link. Never had a problem with either of these.
Things I have tried:
- Many users have stated that the flash latency must be changed before PLL turned on. I have tried manually changing to mode 0 and mode 1
- Tried HSI and HSE as PLL source. HSE looks good on a scope. Neither work.
- Tried erasing the chip and reflashing fresh chip with PLL code.
- Tried many different configurations of PLL multiplier...etc. within the clock configuration tab.
- Tried the example code straight out of the reference manual for the micro on page 732.
- Tried two different micros
- Tried the evaluation board and PLL worked fine up to 48MHz on there...
__HAL_RCC_PLL_ENABLE();
Bricks the program every time.
Here is my configuration code:
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
{
Error_Handler();
}
HAL_RCC_MCOConfig(RCC_MCO, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
}
