Hello @Community member ,
Thank you for your question. As you may know, the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler.
Indeed, there is an equivalent equation to calculate the refresh interval :
In the formula above,
Flsi is equal to an independent 32 kHz internal RC (LSI).
Piwdg_prescaler is the prescaler value.
Niwdg_counterval is the downcounter reload value.
You can configure the two last parameters in STM32CubeMX > Pinout & Configuration > System Core > IWDG > Configuration once the IWDG is activated.
As conclusion, you need to refresh the IWDG before the 12-bit downcounter reaches the zero value. So the Tiwdg time is the maximum delay.
If you have any other questions or suggestions, don't hesitate to ask.
Pierre
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