2023-08-31 01:32 AM
Hi everyone,
I bought a display Riverdi display (RVT70HSSNWC00-B) with a STM32H757XIH6 microcontroller.
I want to setup the FDCAN but without success.
Has anybody already done and could send a sample ?
Thank you in advance.
Solved! Go to Solution.
2024-05-27 11:05 PM
Hi,
Here is my notes for a project test, I hope this will help you :
fdcan.c
/* USER CODE END FDCAN1_Init 1 */
hfdcan1.Instance = FDCAN1;
hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
hfdcan1.Init.AutoRetransmission = DISABLE;
hfdcan1.Init.TransmitPause = DISABLE;
hfdcan1.Init.ProtocolException = DISABLE;
hfdcan1.Init.NominalPrescaler = 16;
hfdcan1.Init.NominalSyncJumpWidth = 1;
hfdcan1.Init.NominalTimeSeg1 = 2;
hfdcan1.Init.NominalTimeSeg2 = 2;
hfdcan1.Init.DataPrescaler = 1;
hfdcan1.Init.DataSyncJumpWidth = 1;
hfdcan1.Init.DataTimeSeg1 = 1;
hfdcan1.Init.DataTimeSeg2 = 1;
hfdcan1.Init.MessageRAMOffset = 0;
hfdcan1.Init.StdFiltersNbr = 2; //un filtre par trame entrante
hfdcan1.Init.ExtFiltersNbr = 0;
hfdcan1.Init.RxFifo0ElmtsNbr = 0;
hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
hfdcan1.Init.RxFifo1ElmtsNbr = 0;
hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
hfdcan1.Init.RxBuffersNbr = 2; //un buffer par trame entrante
hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_12; //8
hfdcan1.Init.TxEventsNbr = 0;
hfdcan1.Init.TxBuffersNbr = 2; //un buffer par trame sortante
hfdcan1.Init.TxFifoQueueElmtsNbr = 0;
hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_12; //8
if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN FDCAN1_Init 2 */
main.c
/* USER CODE BEGIN PV */
FDCAN_FilterTypeDef sFilterConfig; //filtre de la première trame
FDCAN_TxHeaderTypeDef TxHeader; //Première trame sortante
FDCAN_RxHeaderTypeDef RxHeader; //Première trame entrante
uint8_t TxData_Node1_To_Node2[8]={0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}; //data première trame sortante
uint8_t RxData_From_Node2[12]; //data première trame entrante
FDCAN_FilterTypeDef sFilterConfig2; //filtre de la deuxième trame
FDCAN_TxHeaderTypeDef TxHeader2; //deuxième trame sortante
FDCAN_RxHeaderTypeDef RxHeader2; //deuxième trame entrante
uint8_t TxData_Node1_To_Node22[8]={0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}; //data deuxième trame sortante
uint8_t RxData_From_Node22[12]; //data deuxième trame sortante
/* USER CODE END PV */
/* USER CODE BEGIN 2 */
if (BSP_SDRAM_SingleTest() != 0)
{
// Error_Handler();
}
if (CSP_QUADSPI_Init() == HAL_OK) {
CSP_QSPI_EnableMemoryMappedMode();
}
// DEMO_RibusDisplayQuery( );
if (HAL_TIM_PWM_Start(&htim15, TIM_CHANNEL_1) != HAL_OK)
{
/* PWM Generation Error */
Error_Handler();
}
//CODE STM
// Configure Tx buffer message 1
TxHeader.Identifier = 0x1;
TxHeader.IdType = FDCAN_STANDARD_ID;
TxHeader.TxFrameType = FDCAN_DATA_FRAME;
TxHeader.DataLength = FDCAN_DLC_BYTES_12;
TxHeader.ErrorStateIndicator = FDCAN_ESI_ACTIVE;
TxHeader.BitRateSwitch = FDCAN_BRS_ON;
TxHeader.FDFormat = FDCAN_FD_CAN;
TxHeader.TxEventFifoControl = FDCAN_NO_TX_EVENTS;
TxHeader.MessageMarker = 0x0; // Ignore because FDCAN_NO_TX_EVENTS
if(HAL_FDCAN_AddMessageToTxBuffer(&hfdcan1, &TxHeader, TxData_Node1_To_Node2, FDCAN_TX_BUFFER0) != HAL_OK)
{
Error_Handler();
}
// Configure Tx buffer message 2
TxHeader2.Identifier = 0x10;
TxHeader2.IdType = FDCAN_STANDARD_ID;
TxHeader2.TxFrameType = FDCAN_DATA_FRAME;
TxHeader2.DataLength = FDCAN_DLC_BYTES_12;
TxHeader2.ErrorStateIndicator = FDCAN_ESI_ACTIVE;
TxHeader2.BitRateSwitch = FDCAN_BRS_ON;
TxHeader2.FDFormat = FDCAN_FD_CAN;
TxHeader2.TxEventFifoControl = FDCAN_NO_TX_EVENTS;
TxHeader2.MessageMarker = 0x0; // Ignore because FDCAN_NO_TX_EVENTS
if(HAL_FDCAN_AddMessageToTxBuffer(&hfdcan1, &TxHeader2, TxData_Node1_To_Node22, FDCAN_TX_BUFFER1) != HAL_OK)
{
Error_Handler();
}
//Configure standard ID reception filter to Rx buffer 0
sFilterConfig.IdType = FDCAN_STANDARD_ID;
sFilterConfig.FilterIndex = 0;
#if 0
sFilterConfig.FilterType = FDCAN_FILTER_DUAL; // Ignore because FDCAN_FILTER_TO_RXBUFFER
#endif
sFilterConfig.FilterConfig = FDCAN_FILTER_TO_RXBUFFER;
sFilterConfig.FilterID1 = 0x700; // ID Node2
#if 0
sFilterConfig.FilterID2 = 0x0; // Ignore because FDCAN_FILTER_TO_RXBUFFER
#endif
sFilterConfig.RxBufferIndex = 0;
if(HAL_FDCAN_ConfigFilter(&hfdcan1, &sFilterConfig) != HAL_OK)
{
Error_Handler();
}
//Configure standard ID reception filter to Rx buffer 1
sFilterConfig2.IdType = FDCAN_STANDARD_ID;
sFilterConfig2.FilterIndex = 1;
#if 0
sFilterConfig2.FilterType = FDCAN_FILTER_DUAL; // Ignore because FDCAN_FILTER_TO_RXBUFFER
#endif
sFilterConfig2.FilterConfig = FDCAN_FILTER_TO_RXBUFFER;
sFilterConfig2.FilterID1 = 0x2; // ID Node2
#if 0
sFilterConfig2.FilterID2 = 0x0; // Ignore because FDCAN_FILTER_TO_RXBUFFER
#endif
sFilterConfig2.RxBufferIndex = 1;
if(HAL_FDCAN_ConfigFilter(&hfdcan1, &sFilterConfig2) != HAL_OK)
{
Error_Handler();
}
// Start the FDCAN module
if(HAL_FDCAN_Start(&hfdcan1) != HAL_OK)
{
Error_Handler();
}
// Send Tx buffer message 1
if(HAL_FDCAN_EnableTxBufferRequest(&hfdcan1, FDCAN_TX_BUFFER0) != HAL_OK)
{
Error_Handler();
}
// Send Tx buffer message 2
if(HAL_FDCAN_EnableTxBufferRequest(&hfdcan1, FDCAN_TX_BUFFER1) != HAL_OK)
{
Error_Handler();
}
// Polling for transmission complete on buffer index 0
while(HAL_FDCAN_IsTxBufferMessagePending(&hfdcan1, FDCAN_TX_BUFFER0) == 1);
// Polling for reception complete on buffer index 0
while(HAL_FDCAN_IsRxBufferMessageAvailable(&hfdcan1, FDCAN_RX_BUFFER0) == 0);
// Polling for transmission complete on buffer index 1
while(HAL_FDCAN_IsTxBufferMessagePending(&hfdcan1, FDCAN_TX_BUFFER1) == 1);
// Polling for reception complete on buffer index 1
while(HAL_FDCAN_IsRxBufferMessageAvailable(&hfdcan1, FDCAN_RX_BUFFER1) == 0);
// Retrieve message from Rx buffer 0
if(HAL_FDCAN_GetRxMessage(&hfdcan1, FDCAN_RX_BUFFER0, &RxHeader, RxData_From_Node2) != HAL_OK)
{
Error_Handler();
}
// Retrieve message from Rx buffer 1
if(HAL_FDCAN_GetRxMessage(&hfdcan1, FDCAN_RX_BUFFER1, &RxHeader2, RxData_From_Node22) != HAL_OK)
{
Error_Handler();
}
//FIN CODE STM
/* USER CODE END 2 */
Model.cpp
#include <fdcan.h>
extern FDCAN_RxHeaderTypeDef RxHeader;
extern FDCAN_TxHeaderTypeDef TxHeader;
extern uint8_t RxData_From_Node2[12];
extern uint8_t TxData_Node1_To_Node2[12];
extern FDCAN_RxHeaderTypeDef RxHeader2;
extern FDCAN_TxHeaderTypeDef TxHeader2;
extern uint8_t RxData_From_Node22[12];
extern uint8_t TxData_Node1_To_Node22[12];
//ajout message au TXBuffer0
if(HAL_FDCAN_AddMessageToTxBuffer(&hfdcan1, &TxHeader, TxData_Node1_To_Node2, FDCAN_TX_BUFFER0) != HAL_OK)
{
//Error_Handler();
}
// Send Tx buffer message 1
if(HAL_FDCAN_EnableTxBufferRequest(&hfdcan1, FDCAN_TX_BUFFER0) != HAL_OK)
{
//Error_Handler();
}
//ajout message au TXBuffer1
if(HAL_FDCAN_AddMessageToTxBuffer(&hfdcan1, &TxHeader2, TxData_Node1_To_Node22, FDCAN_TX_BUFFER1) != HAL_OK)
{
//Error_Handler();
}
// Send Tx buffer message 2
if(HAL_FDCAN_EnableTxBufferRequest(&hfdcan1, FDCAN_TX_BUFFER1) != HAL_OK)
{
//Error_Handler();
}
// Retrieve message from Rx buffer 0
if(HAL_FDCAN_GetRxMessage(&hfdcan1, FDCAN_RX_BUFFER0, &RxHeader, RxData_From_Node2) != HAL_OK)
{
//Error_Handler();
}
// Retrieve message from Rx buffer 1
if(HAL_FDCAN_GetRxMessage(&hfdcan1, FDCAN_RX_BUFFER1, &RxHeader2, RxData_From_Node22) != HAL_OK)
{
//Error_Handler();
}