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Clock configuration issue with HSI16

newtonbytes
Associate

Hi all,

I'm designing a custom board using the STM32L151C8. The CubeIDE is giving me an error with the clock configuration, highlighting the HSI input on the PLL Source Mux.

The following image shows the PLLMul = x6 which is the only option to make the 48Mhz clocks box not pink. (Also, 16MHz * 6 = 96Mhz? Why is the output of the 48MHz?).

Screenshot (254).png

On p79/130 of  the STM32L151C8 datasheet, under section 6.3.8 PLL characteristics the max PLL frequency is 32Mhz. For a 16Mhz input, the PLLMul must then be 2x but this is not an option?

Screenshot (257).png

I was unable to find any documentation on where the error of the Clock Config tab can be read/displayed? Any help on how to resolve this would be highly appreciated.

Thanks!

2 REPLIES 2

>> The following image shows the PLLMul = x6 which is the only option to make the 48Mhz clocks box not pink. (Also, 16MHz * 6 = 96Mhz? Why is the output of the 48MHz?).

Yes, because there's a DIV2 in the clock path, and 48 MHz is the only thing supported for USB ?

Presumably if you're not using USB you can play any games you want with the PLL's manually

HSI16 routes directly into the primary PLL, you can use that to clock the MCU at whatever speeds you want there.

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You're looking at a different data sheet

https://www.st.com/resource/en/datasheet/stm32l151c8.pdf

The max out for the primary PLL, and the MCU is 32 MHz. Arguably the MCU can go faster, but the FLASH is slow, so honestly 32 MHz at 1-wait state is probably marginally faster than 24 MHz at 0-wait states.

The VCO is rated at 96 MHz (it generates pulses), the DIV2 ensures 50/50 duty which the MCU and USB need for their internal logic to work, as it uses both edges

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