Waking up Cortex M4 from Cortex A7-0 in STM32MP1 for Bare metal.

[Srikanth1]

we are developing the application by using STM32MP1 processor in bare metal.

we are able to wake up Cortex A7-1 from Cortex A7-0 both are working fine. Now we tried to wake up Cortex M4 from Cortex A7-0,But we are unable to wakeup Cortex M4 from Cortex A7-0.

Individually Cortex M4 is working fine with JTAG .and we can able to wake up Cortex M4 from UBOOT By using RPROC commands .

But in our application we need to wake up Cortex M4 from cortex A7-0 in bare metal. Can you give the sequence of waking up cortex-m4 from Cortex-A7-0 in Bare metal.

So please help us in this.

[PatrickF]

Hi,

Maybe share more information than "we are unable to wakeup Cortex M4 from Cortex A7-0" could help.

What did not work ? What did you tried and what are the issue ?

As you are in bare-metal, did you try to debug both A7 and M4 together using JTAG (e.g. using Lauterbach Trace32 tool) ?

Did you check HDP view of internal power control signals to confirm what is going wrong?

Wake-up mechanism depend on which low power mode the Cortex-M4 is:

For Run or Csleep, any NVIC interrupts could be used.

For CStop, which requires EXTI, please refer to RefMan "STM32MP157 EXTI Events".

I think you could use IPCC (EXTI61 or 62), HSEM_IT2 (EXTI64) or Cortex-A SEV (EXTI66) which could be triggered from Cortex-A7 actions and, when set in EXTI, could wakeup Cortex-M4 (and as well trigger NVIC interrupts in Run or CSleep).

Regards.

[Srikanth1]

Hi,

Thanks for the reply

We referred 10.3.14 chapter in stm32mp157a processor reference manual for waking up Cortex-M4 in stm32mp157a.

Below are the steps we followed

1.Clearing the MCU_BOOT bit in RCC Global control Register(0x5000010C)

2.Making MCU_RST low in RCC Global Reset control Set_Register(Address:0x50000404)

3.We are coping Cortex-M4 bin file in RETRAM(Address:0x38000000).

4.We are setting Coprocessor state(C_RUN) in TAMP Backup Register(0x5C00A148).

6.We are setting Coprocessor Resource Table address as 0 in TAMP Backup Register(0x5C00A144).

Is it Correct way to wakeup cortex-M4 from Coretx-A7 in stm32mp157a processor?

If not ,we want actual procedure for waking up cortex-M4 from Cortex-A7 in stm2mp157a processor.

regards

srikanth

[PatrickF]

Hi @Srikanth​ 

sequence could be :

1. RCC_MP_GCR.BOOT_MCU = 0 (should be the case by default after a system reset)
2. RCC_MP_GRSTCSETR.MCURST = 1 (not needed after a system reset)
3. Load Cortex-M4 binary in RETRAM and in SRAMx if needed (ensure correct value for initial SP and reset vector, which should be an odd value by definition for Cortex-M4). Refer also to PM0214
4. RCC_MP_GCR.BOOT_MCU = 1

No need to play with backup registers as you are in bare-metal.

Regards.

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[PatrickF]

Btw, seems similar question that https://community.st.com/s/question/0D53W000020GKDQSA4/how-do-i-boot-cortex-m4-in-cortex-a7-in-baremetal

[Srikanth1]

Hi,

Thanks for the reply.

We followed

1. RCC_MP_GCR.BOOT_MCU = 0 (should be the case by default after a system reset)
2. RCC_MP_GRSTCSETR.MCURST = 1 (not needed after a system reset)
3. Load Cortex-M4 binary in RETRAM(we kept the cortex M4 binary in RETRAM).
4. RCC_MP_GCR.BOOT_MCU = 1

But M4 code is not running.

Is there any steps need to take care of M4 code?

Is there any other procedure for waking up M4 from A7?

[PatrickF]

This should be ok.

Once started, did you success to debug your M4 code with JTAG to see what is going wrong ? Maybe a missing init on some clocks or resources used by your code.

If RETRAM is declared as cacheable form A7 side, you should manage the data cache to be sure data are effectively written in the RETRAM memory.

Note that loading Cortex-M4 in RETRAM from A7 should be done from address 0x38000000 onward, whereas the Cortex-M4 code should be compiled with vector table in 0 and code execution in the RETRAM range 0 to 0xFFFF.

Btw, did you check that you have right SP initial value and Reset vector (must be an odd value) at respectively address 0x38000000 and 0x38000004 (or 0 and 4 seen by Cortex-M4)?

Regards

[Srikanth1]

Hi,

Thanks for the reply.

Please note that cortex-M4 is not in our control. Hence we may not Execute any instruction in Cortex-M4.

We have only one option is by writing registers in cortex-A7 to put cortex-m4 in Csleep mode.

Please let us know the method.

[PatrickF]

Hi,

I'm puzzled,

I confirm the sequence to load binary and run code on M4 works (just tested again on my side).

Note that If you are in development boot mode (BOOT=0b100), please note that M4 is started by BootROM in an infinite loop (in opposition to all other modes where M4 is kept in reset). So in that particular case, you should do this sequence :

1. RCC_MP_GCR.BOOT_MCU = 0 (define M4 in Hold boot)
2. RCC_MP_GRSTCSETR.MCURST = 1 (reset M4)
3. Load Cortex-M4 binary in RETRAM (and SRAMs if needed)
4. RCC_MP_GCR.BOOT_MCU = 1

In all other Boot modes, this sequence is enough:

1. Load Cortex-M4 binary in RETRAM (and SRAMs if needed)
2. RCC_MP_GCR.BOOT_MCU = 1

Note that when M4 is in reset in HOLD_BOOT mode, it's state is ignored and all platform low power mode are available

Regards.