2020-11-23 05:26 AM
Hi,
I am trying to use the lan9303 chip in mdio managed mode on a stm32mp157-based board.
I configured the Device tree according to https://kernel.googlesource.com/pub/scm/linux/kernel/git/next/linux-next/+/refs/heads/akpm-base/Documentation/devicetree/bindings/net/dsa/lan9303.txt
and my .dts file looks like this:
#include "stm32mp157.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15-qsmp.dtsi"
/ {
model = "Ka-Ro electronics GmbH QSMP-1570 module on HSW board v1";
compatible = "karo,stm32mp157c-qsmp-1570", "st,stm32mp157";
};
&gpu {
status = "okay";
};
ðernet0 {
status = "okay";
pinctrl-0 = <ðernet0_rmii_pins_a>;
pinctrl-1 = <ðernet0_rmii_pins_sleep_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rmii";
max-speed = <1000>;
phy-handle = <&switch>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
switch: switch-phy@0 {
compatible = "smsc,lan9303-mdio";
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <ðernet0>;
};
port@1 { /* external port 1 */
reg = <1>;
label = "lan1";
};
port@2 { /* external port 2 */
reg = <2>;
label = "lan2";
};
};
};
};
};
On boot the kernel recognizes the lan9303 driver and the ports lan1 and lan2 but fails to find a PHY. I will attach the output.
The ethernet node in the flattened device tree looks like this:
ethernet@5800a000 {
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
reg = <0x5800a000 0x00002000>;
reg-names = "stmmaceth";
interrupts = <0x00000000 0x0000003d 0x00000004>;
interrupt-names = "macirq";
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx", "eth-ck", "ethstp";
clocks = <0x00000004 0x00000069 0x00000004 0x00000067 0x00000004 0x00000068 0x00000004 0x0 000007b 0x00000004 0x00000070>;
st,syscon = <0x00000003 0x00000004>;
snps,mixed-burst;
snps,pbl = <0x00000002>;
snps,en-tx-lpi-clockgating;
snps,axi-config = <0x00000028>;
snps,tso;
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <0x00000029>;
pinctrl-1 = <0x0000002a>;
phy-handle = <0x0000002b>;
phy-mode = "rmii";
max-speed = <0x000003e8>;
phandle = <0x0000002d>;
mdio0 {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
compatible = "snps,dwmac-mdio";
reset-gpios = <0x0000002c 0x00000004 0x00000001>;
reset-delay-us = <0x00002710>;
post-reset-delay-us = <0x000003e8>;
ethernet-phy@3 {
compatible = "ethernet-phy-id0022.1622";
reg = <0x00000003>;
interrupt-parent = <0x0000002c>;
interrupts = <0x00000009 0x00000002>;
rxd0-skew-ps = <0x000001aa>;
rxd1-skew-ps = <0x000001a9>;
rxd2-skew-ps = <0x000001a3>;
rxd3-skew-ps = <0x0000018e>;
txd0-skew-ps = <0x0000013d>;
txd1-skew-ps = <0x0000013c>;
txd2-skew-ps = <0x0000015b>;
txd3-skew-ps = <0x0000018b>;
txen-skew-ps = <0x000001b3>;
rxdv-skew-ps = <0x00000198>;
rxc-skew-ps = <0x00000384>;
txc-skew-ps = <0x0000076c>;
};
switch-phy@0 {
compatible = "smsc,lan9303-mdio";
reg = <0x00000000>;
phandle = <0x0000002b>;
ports {
#address-cells = <0x00000001>;
#size-cells = <0x00000000>;
port@0 {
reg = <0x00000000>;
label = "cpu";
ethernet = <0x0000002d>;
};
port@1 {
reg = <0x00000001>;
label = "lan1";
};
port@2 {
reg = <0x00000002>;
label = "lan2";
};
};
};
};
};
I checked all the Pin connections and everything seems to be ok.
Does anybody have any experience with the lan9303 Chip in mdio-managed mode?
Thanks in advance
2020-11-27 05:24 AM
Hi @NHuhs.2394 ,
In your log, it seems that an interrupt-names is missing :
[ 4.349668] stm32-dwmac 5800a000.ethernet: IRQ eth_wake_irq not found
BR,
Christophe
2020-11-30 03:03 AM
Hi Christophe,
I added the interrupt following the guide at : https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration#RMII_with_Crystal_on_PHY_-28Reference_clock_-28standard_RMII_clock_name-29_is_provided_by_a_Phy_Crystal-29
Still no success.
Still getting a message about a missing interrupt, but this one shouldn't be needed. And the Eth_Clock should be provided by the lan chip.
I read in another forum, that some ST Boards have PHY Address 0 reserved for internal purposes.
DOes somebody know if thats the case for the STM32MP157c?(I couldn't find anything) In that case I would have to change my Board layout.
2020-11-30 04:23 AM
Hi @NHuhs.2394 ,
By having a look into your log, ethernet seems broken even at u-boot stage:
Net: MAC addr from fuse: 00:0c:c6:88:4f:bc
ethernet@5800a000: EQOS_DMA_MODE_SWR stuck
No ethernet found.
Before investigating the issue on the kernel, I would recommand to fix the one from u-boot, or temporally disable ethernet feature in u-boot. Then ethernet from kernel will be able to init from an HW clean state.
I didn't see any reset entry in your node : how is manage the reset of the switch ?
In the documentation, it's managed like that:
reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
reset-duration = <200>;
Could you also please tell me on which MMDV version you are ? (MMDV-1.x.x or MMDV-2.x.x ?)
BR,
Christophe
2020-11-30 05:34 AM
Thanks, I will try to disable ethernet in u-boot. Do you know if its possible to do it directly in u-boot or do I have to modify the Code/Device Tree?
The Reset of the switch is directly connected to a reset button. Not to any GPIO. The reset-gpios parameter is called "optional" in the doc, and it seemed to work on similar boards.
I am sorry but I don't know what you mean with MMDV.
2021-11-08 04:33 AM
The problem was solved? Can You add some comments?
2021-11-10 12:28 AM
Yes the problem was solved.
What I did was following things:
ðernet0 {
status = "okay";
pinctrl-0 = <ðernet0_rmii_pins_a>;
pinctrl-1 = <ðernet0_rmii_pins_sleep_a>;
pinctrl-names = "default", "sleep";
phy-mode = "rmii";
};
&pinctrl {
ethernet0_rmii_pins_a: rmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
<STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
<STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */
<STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
<STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
<STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
bias-disable;
};
};
ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
<STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
<STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
<STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
};
};
};
&mdio0 {
reset-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
reset-delay-us = <10000>;
post-reset-delay-us = <1000>;
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622";
reg = <0>;
};
};
The lan9303 acts as a switch and I am able to use both LAN-Ports .
2021-11-10 12:43 AM
Thanks a lot, I try it. The reset is mandatory?
Best Regards
2021-11-10 07:03 AM
I have a follwing error
[ 2.816259] stm32-dwmac 5800a000.ethernet: IRQ eth_lpi not found
[ 2.821084] stm32-dwmac 5800a000.ethernet: PTP uses main clock
[ 2.826849] stm32-dwmac 5800a000.ethernet: no reset control found
[ 2.833593] stm32-dwmac 5800a000.ethernet: User ID: 0x40, Synopsys ID: 0x42
[ 2.839981] stm32-dwmac 5800a000.ethernet: DWMAC4/5
[ 2.845039] stm32-dwmac 5800a000.ethernet: DMA HW capability register supported
[ 2.852384] stm32-dwmac 5800a000.ethernet: RX Checksum Offload Engine supported
[ 2.859817] stm32-dwmac 5800a000.ethernet: TX Checksum insertion supported
[ 2.866775] stm32-dwmac 5800a000.ethernet: Wake-Up On Lan supported
[ 2.873222] stm32-dwmac 5800a000.ethernet: TSO supported
[ 2.878443] stm32-dwmac 5800a000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[ 2.886415] stm32-dwmac 5800a000.ethernet: device MAC address 32:a1:b4:b2:49:cf
[ 2.893792] stm32-dwmac 5800a000.ethernet: Enabled Flow TC (entries=2)
[ 2.900364] stm32-dwmac 5800a000.ethernet: TSO feature enabled
[ 2.906287] stm32-dwmac 5800a000.ethernet: Using 32 bits DMA width
[ 44.658224] using random self ethernet address
[ 44.661279] using random host ethernet address
[ 45.253396] stm32-dwmac 5800a000.ethernet eth0: PHY [stmmac-0:00] driver [Generic PHY] (irq=POLL)
[ 46.283123] stm32-dwmac 5800a000.ethernet: Failed to reset the dma
[ 46.287939] stm32-dwmac 5800a000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
[ 46.313146] stm32-dwmac 5800a000.ethernet eth0: stmmac_open: Hw setup failed
but is much better I have before
2021-11-13 06:37 AM
After some modification I get
[ 3.039706] libphy: stmmac: probed
[ 3.041706] mdio_bus stmmac-0:00: attached PHY driver [unbound] (mii_bus:phy_addr=stmmac-0:00, irq=POLL)
[ 3.051566] SMSC LAN911x Internal PHY stmmac-0:01: attached PHY driver [SMSC LAN911x Internal PHY] (mii_bus:phy_addr=stmmac-0:01, irq=POLL)
[ 3.064334] SMSC LAN911x Internal PHY stmmac-0:02: attached PHY driver [SMSC LAN911x Internal PHY] (mii_bus:phy_addr=stmmac-0:02, irq=POLL)
[ 3.076816] mdio_bus stmmac-0:10: attached PHY driver [unbound] (mii_bus:phy_addr=stmmac-0:10, irq=POLL)
[ 3.086446] mdio_bus stmmac-0:11: attached PHY driver [unbound] (mii_bus:phy_addr=stmmac-0:11, irq=POLL)
[ 3.096064] mdio_bus stmmac-0:12: attached PHY driver [unbound] (mii_bus:phy_addr=stmmac-0:12, irq=POLL)
[ 3.105695] mdio_bus stmmac-0:13: attached PHY driver [unbound] (mii_bus:phy_addr=stmmac-0:13, irq=POLL)
[ 3.115341] mdio_bus stmmac-0:14: attached PHY driver [unbound] (mii_bus:phy_addr=stmmac-0:14, irq=POLL)
[ 3.124960] mdio_bus stmmac-0:15: attached PHY driver [unbound] (mii_bus:phy_addr=stmmac-0:15, irq=POLL)
[ 3.134592] mdio_bus stmmac-0:16: attached PHY driver [unbound] (mii_bus:phy_addr=stmmac-0:16, irq=POLL)
[ 3.144235] mdio_bus stmmac-0:17: attached PHY driver [unbound] (mii_bus:phy_addr=stmmac-0:17, irq=POLL)
[ 3.153857] mdio_bus stmmac-0:18: attached PHY driver [unbound] (mii_bus:phy_addr=stmmac-0:18, irq=POLL)
[ 3.163489] mdio_bus stmmac-0:19: attached PHY driver [unbound] (mii_bus:phy_addr=stmmac-0:19, irq=POLL)
[ 3.173122] mdio_bus stmmac-0:1a: attached PHY driver [unbound] (mii_bus:phy_addr=stmmac-0:1a, irq=POLL)
[ 3.182739] mdio_bus stmmac-0:1b: attached PHY driver [unbound] (mii_bus:phy_addr=stmmac-0:1b, irq=POLL)
[ 3.192386] mdio_bus stmmac-0:1c: attached PHY driver [unbound] (mii_bus:phy_addr=stmmac-0:1c, irq=POLL)
[ 3.202024] mdio_bus stmmac-0:1d: attached PHY driver [unbound] (mii_bus:phy_addr=stmmac-0:1d, irq=POLL)
[ 3.211675] mdio_bus stmmac-0:1e: attached PHY driver [unbound] (mii_bus:phy_addr=stmmac-0:1e, irq=POLL)
[ 3.221290] mdio_bus stmmac-0:1f: attached PHY driver [unbound] (mii_bus:phy_addr=stmmac-0:1f, irq=POLL)
[ 16.953699] stm32-dwmac 5800a000.ethernet eth0: PHY [stmmac-0:00] driver [Generic PHY] (irq=POLL)
[ 17.987895] stm32-dwmac 5800a000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
[ 18.013087] stm32-dwmac 5800a000.ethernet eth0: stmmac_open: Hw setup failed
Still the same problem with DMA. What is missing, which clock is missing?