Hi,
I am debugging the STM32MP257F-EV1 board with a debugger via JTAG/SWD. The kernel version is 6.1.82.
Since the A35 cores are in break state/stopped during debugging, I want to disable the watchdog timer on U-Boot/Linux.
I have tried the following ways to stop the watchdog timer:
1. Disable the watchdog via the dts files in case of Linux. I don't think it is that simple. The watchdog still resets the system when the Linux Core is stopped.
2. I have been trying to Freeze the watchdog by modifying Bit FZ_IWDG1 of register RCC_IWDGC1FZSETR.
I have set the following registers to enable writing to Bit FZ_IWDG1;
RCC_SECCFGR2: 0
RCC_PRIVCFGR2: 0
RCC_RCFGLOCKR2: 0
RCC_R70CIDCFGR/RCC_RxCIDCFGR: Bit SEM_EN=1
RCC_R70SEMCR/RCC_RxSEMCR: Bit SEM_MUTEX=1
But I am unable to change the Bit FZ_IWDG1.
Please let me know how if I am missing any settings.
Also, please let me know how the watchdog timer can be frozen/stopped.
Thank you.
