STM32MP1 ethernet error message

[rmaki.1]

I have a question about the Starter Package.

When I start STM32MP157x-EV1 (+en.FLASH-stm32mp1-openstlinux-5-4-dunfell-mp1-20-11-12), I get the following log

root@stm32mp1:~# dmesg | grep ether

[   1.642061] stm32-dwmac 5800a000.ethernet: PTP uses main clock

[   1.646451] stm32-dwmac 5800a000.ethernet: no reset control found

[   1.652761] stm32-dwmac 5800a000.ethernet: No phy clock provided...

[   1.659898] stm32-dwmac 5800a000.ethernet: User ID: 0x40, Synopsys ID: 0x42

[   1.665789] stm32-dwmac 5800a000.ethernet:  DWMAC4/5

[   1.670828] stm32-dwmac 5800a000.ethernet: DMA HW capability register suppord

[   1.678090] stm32-dwmac 5800a000.ethernet: RX Checksum Offload Engine suppord

[   1.685379] stm32-dwmac 5800a000.ethernet: TX Checksum insertion supported  

[   1.692284] stm32-dwmac 5800a000.ethernet: Wake-Up On Lan supported         

[   1.698555] stm32-dwmac 5800a000.ethernet: TSO supported                    

[   1.703846] stm32-dwmac 5800a000.ethernet: Enable RX Mitigation via HW Watchr

[   1.711711] stm32-dwmac 5800a000.ethernet: TSO feature enabled                       

[  10.949696] stm32-dwmac 5800a000.ethernet eth0: No Safety Features support fd

[  10.977731] stm32-dwmac 5800a000.ethernet eth0: IEEE 1588-2008 Advanced Timed

[  11.042607] stm32-dwmac 5800a000.ethernet eth0: registered PTP clock        

I suspect that the reason for the "no reset control found" message above is that the compatible of the mdio part under ethernet in the devicetree is as follows

root@stm32mp1:~# cat /proc/device-tree/soc/ethernet@5800a000/mdio0/compatible  

snps,dwmac-mdio

It looks like the ethernet PHY is listed as being from synopsys, even though it is actually from realtek.

This description is also the same in the devicetree of the developer package

Is the above assumption correct?

If my guess is correct, could you tell me what the ethernet part of the devicetree should be?

[PatrickF · Accepted solution]

Hi, I'm not specialist of Ethernet Linux driver, but i will try to give you some answers.

Could you also precise if you are facing issues or if you are just asking for clarifications ?

The Ethernet is working out of the box with EV1 (or DK1/DK2) with starter package.

Synopsys (dwmac) is the GMAC inside the STM32MP15x (named ETH in the Reference Manual).

The PHY itself is listed later in my grep. It is RTL8211E for STM32MP15x-EV1.

The 'No phy clock provided' is probably only a driver information message and not an error.

Here is my own "dmesg | grep ether" on EV1 board with Ethernet connected, result is very close than your:

(I added a ping to show the Ethernet is working)

root@stm32mp1:~# dmesg | grep ether
[    1.244781] usbcore: registered new interface driver cdc_ether
[    2.681360] stm32-dwmac 5800a000.ethernet: IRQ eth_lpi not found
[    2.686055] stm32-dwmac 5800a000.ethernet: PTP uses main clock
[    2.691853] stm32-dwmac 5800a000.ethernet: no reset control found
[    2.697862] stm32-dwmac 5800a000.ethernet: No phy clock provided...
[    2.704742] stm32-dwmac 5800a000.ethernet: User ID: 0x40, Synopsys ID: 0x42
[    2.711128] stm32-dwmac 5800a000.ethernet:   DWMAC4/5
[    2.716012] stm32-dwmac 5800a000.ethernet: DMA HW capability register supported
[    2.723348] stm32-dwmac 5800a000.ethernet: RX Checksum Offload Engine supported
[    2.730646] stm32-dwmac 5800a000.ethernet: TX Checksum insertion supported
[    2.737500] stm32-dwmac 5800a000.ethernet: Wake-Up On Lan supported
[    2.743783] stm32-dwmac 5800a000.ethernet: TSO supported
[    2.749075] stm32-dwmac 5800a000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[    2.756930] stm32-dwmac 5800a000.ethernet: TSO feature enabled
[   74.026904] using random self ethernet address
[   74.039531] using random host ethernet address
[   74.500704] stm32-dwmac 5800a000.ethernet eth0: PHY [stmmac-0:00] driver [RTL8211E Gigabit Ethernet]
[   74.572776] stm32-dwmac 5800a000.ethernet eth0: No Safety Features support found
[   74.595505] stm32-dwmac 5800a000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported
[   74.620923] stm32-dwmac 5800a000.ethernet eth0: registered PTP clock
[   74.625839] stm32-dwmac 5800a000.ethernet eth0: configuring for phy/rgmii-id link mode
[   78.811114] stm32-dwmac 5800a000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
root@stm32mp1:~# ping www.st.com -c 3
PING www.st.com.wcdnga.com (163.171.131.240) 56(84) bytes of data.
64 bytes from 163.171.131.240: icmp_seq=1 ttl=56 time=15.8 ms
64 bytes from 163.171.131.240: icmp_seq=2 ttl=56 time=16.4 ms
64 bytes from 163.171.131.240: icmp_seq=3 ttl=56 time=16.6 ms
 
--- www.st.com.wcdnga.com ping statistics ---
3 packets transmitted, 3 received, 0% packet loss, time 7299ms
rtt min/avg/max/mdev = 15.843/16.265/16.571/0.308 ms

Regards.

[rmaki.1]

Thank you for your reply.

I am just asking for clarifications.

Thanks to your answer, I understand that the description of "snps" in "compatible" is for GMAC, not PHY.

The information about the Ethernet PHY module (e.g. realtek,RTL8211) is not mentioned anywhere in the devicetree, is it correct that this is because the generic driver can read this information from the module if it follows some standard?

[PatrickF]

I agree, the exact PHY reference is not in the DT.

https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration

For the auto-selection of the PHY driver, I think this is part of Linux linux kernel (assuming the driver is present in the kernel). But I'm far to be expert on that.

Regards.

[rmaki.1]

Thank you for your kind answer.

I understand.​