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Regarding Timer Sharing Between A7 and M4 Core

meme002
Associate III

Hello @PatrickF ,


Hope all is well.


I need to access STGEN both in A7 core as well as M4 core. I have seen some previous posts related to STGENR register access.

Credit to PatrickF for this code.

#define STGENR_CNTCVL_OFF 0x0000 #define STGENR_CNTCVU_OFF 0x0004 #define STGENR_CNTCVL (*(uint32_t *) (STGENR_BASE + STGENR_CNTCVL_OFF)) #define STGENR_CNTCVU (*(uint32_t *) (STGENR_BASE + STGENR_CNTCVU_OFF))   uint32_t cntr_upper, cntr_lower; uint64_t cntr;   __HAL_RCC_STGENRO_CLK_ENABLE(); do { cntr_upper = STGENR_CNTCVU; cntr_lower = STGENR_CNTCVL; } while (STGENR_CNTCVU != cntr_upper);   cntr = ((uint64_t)cntr_upper << 32) + (uint64_t)cntr_lower;

I did not implement the above code, but I was trying to see if I can read STGENR from A7 using Devmem2.

I found STGENR_BASE from the manual which is 0x5A005000. I used devmem2 tool to read the lower counter (address offset = 0x0000) and upper counter(address offset = 0x0004)

The devmem2 values for both are 0x0. I am not sure why I keep getting that. I was under the impression that STGEN keeps running when the STM32 mp157d-dk1 is booted and the counter should keep incrementing.

I did check in my clock configuration that STGEN is set to 24 Mhz (HSE) and using the command below I can see arch_sys_counter, which is based of STGEN can be seen. This was taken from this post.

 

cat /sys/devices/system/clocksource/clocksource0/available_clocksource 
ksource arch_sys_counter

 

1 ACCEPTED SOLUTION

Accepted Solutions
PatrickF
ST Employee

Hi,

devmem2 is only for debug/trial purposes.

Nevertheless, you should enabled the bus clock before access it

try:

# set STGRENROEN bit in RCC_MP_APB4_ENSETR
devmem2 0x50000200 w 0x00100000
# read counter
devmem2 0x5A005000 w

PatrickF_0-1722324350707.png

Regards.

 

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.

View solution in original post

2 REPLIES 2
PatrickF
ST Employee

Hi,

devmem2 is only for debug/trial purposes.

Nevertheless, you should enabled the bus clock before access it

try:

# set STGRENROEN bit in RCC_MP_APB4_ENSETR
devmem2 0x50000200 w 0x00100000
# read counter
devmem2 0x5A005000 w

PatrickF_0-1722324350707.png

Regards.

 

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.

Thanks for quick reply. This is just for trial purposes. Later I will be using mmap tool from linux user land to interface the timer for timestamp.

 

Thanks,

Meme