qaudspi spi-nand flash device tree for tf-a and u-boot

[ASkri.1]

Hi, Everybody!

Could anyone help with correct device tree for qspi-nand flash. I can't see any activity on pins connected to flash. If I try to boot from spi-nand with BOOT0..2 set to 1, I can see clear SPI transactions... So, flash connection looks correct.

Flash type is MT29F1G01ABAFDWB

Connected to following pins:

PF10 - CLK

PB6 - NCS

PF8 - IO0

PF9 - IO1

PF7 - IO2

PF6 - IO3

TF-a device tree:

pinctrl node:
 
	qspi_bk1_pins_a: qspi-bk1-0 {
 
		pins1 {
 
			pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
 
				 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
 
				 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
 
				 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
 
			bias-disable;
 
			drive-push-pull;
 
			slew-rate = <1>;
 
		};
 
 
 
		pins2 {
 
			pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
 
			bias-pull-up;
 
			drive-push-pull;
 
			slew-rate = <1>;
 
		};
 
	};
 
 
 
	qspi_clk_pins_a: qspi-clk-0 {
 
		pins {
 
			pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
 
			bias-disable;
 
			drive-push-pull;
 
			slew-rate = <3>;
 
		};
 
	};
 
 
 
qspi node:
 
 
 
&qspi {
 
	pinctrl-names = "default";
 
	pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
 
	reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
 
	#address-cells = <1>;           
 
	#size-cells = <0>;
 
	status = "okay";
 
 
 
	flash0: mt29f2g01abagd@0 {
 
		compatible = "spi-nand";
 
		reg = <0>;
 
		spi-rx-bus-width = <4>;
 
		spi-tx-bus-width = <4>;
 
		spi-max-frequency = <64000000>;
 
		#address-cells = <1>;
 
		#size-cells = <1>;
 
	};
 
};
 
 
 
u-boot device tree:
 
 
 
	qspi_clk_pins_a: qspi-clk-0 {
 
		u-boot,dm-pre-reloc;
 
		pins {
 
  		u-boot,dm-pre-reloc;
 
			pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
 
			bias-disable;
 
			drive-push-pull;
 
			slew-rate = <3>;
 
		};
 
	};
 
 
 
	qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
 
		u-boot,dm-pre-reloc;
 
		pins {
 
   		u-boot,dm-pre-reloc;
 
 			pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
 
		};
 
	};
 
 
 
	qspi_bk1_pins_a: qspi-bk1-0 {
 
		u-boot,dm-pre-reloc;
 
		pins1 {
 
  		u-boot,dm-pre-reloc;
 
			pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
 
				 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
 
				 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
 
				 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
 
			bias-disable;
 
			drive-push-pull;
 
			slew-rate = <1>;
 
		};
 
		pins2 {
 
    		u-boot,dm-pre-reloc;
 
			pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
 
			bias-pull-up;
 
			drive-push-pull;
 
			slew-rate = <1>;
 
		};
 
	};
 
 
 
	qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
 
		u-boot,dm-pre-reloc;
 
		pins {
 
   		u-boot,dm-pre-reloc;
 
			pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
 
				 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
 
				 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
 
				 <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
 
				 <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
 
		};
 
	};
 
 
 
 
 
&qspi {
 
	pinctrl-names = "default", "sleep";
 
	pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
 
	pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
 
	reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
 
	#address-cells = <1>;
 
	#size-cells = <0>;
 
	status = "okay";
 
 
 
	flash0: mt29f2g01abagd@0 {
 
		compatible = "spi-nand";
 
		reg = <0>;
 
		spi-rx-bus-width = <4>;
 
		spi-tx-bus-width = <4>;
 
		spi-max-frequency = <64000000>;
 
		#address-cells = <1>;
 
		#size-cells = <1>;
 
	};
 
};
 

U-boot output:

U-Boot 2020.01-stm32mp-r1 (Jan 06 2020 - 20:56:31 +0000)

CPU: STM32MP157DAB Rev.Z

Model: STMicroelectronics STM32MP157A-DK1 STM32CubeMX board

Board: stm32mp1 in trusted mode (st,stm32mp157a-stm32mp151-dk1-mx)

DRAM: 512 MiB

Clocks:

- MPU : 800 MHz

- MCU : 208.878 MHz

- AXI : 266.500 MHz

- PER : 24 MHz

- DDR : 533 MHz

WDT:  Started with servicing (32s timeout)

NAND: 0 MiB

MMC:  STM32 SD/MMC: 0

In:  serial

Out:  serial

Err:  serial

invalid MAC address in OTP 00:00:00:00:00:00

stm32 vrefbuf timed out: -110

adc@0: can't enable vdd-supply!board_check_usb_power: single shot failed for adc@0[18]!

Net:

Error: ethernet@5800a000 address not set.

No ethernet found.

Hit any key to stop autoboot: 0

Boot over usb0!

unknown raw ID d7f41b58

Error: MTD device spi-nand0 not found

DFU alt info setting: done

crq->brequest:0x0

Reset requested

#

UPLOAD ... done

Ctrl+C to exit ...

I'm completely stucked here...

Looking forward for any hints and suggestions.

Thank you in advance

Looking forward for your reply

[PatrickF]

Hi,

please check if you have the CLK_QSPI_ACLK in the &rcc node (TF-A Device Tree).

Regards. 

[ASkri.1]

Hi, Patrick! Thank you very much for your reply. There are more details: 1. Yes, of course we have CLK_QSPI_ACLK definition on tf-a's &rcc_node; 2. Now I can see activity on SPI pins. 3. After booting to u-boot and issuing following commands: mtdparts sf probe I've got following error message: STM32MP> sf probe unknown raw ID d7f37c30 Failed to initialize SPI flash at 0:0 (error -524) while executing sf probe commands I can see SPI-pins activity. Hardware looks ok, because spi-frequency is now set to 4Mhz and the result is the same at 2Mhz and at 48Mhz... But d7f37c30 is NOT flash ID installed - I have MT29F1G01ABAFDWB (ID: 0x2c14) - it is closest to ST examples I've found. I didn't find any NAND compatibility list, so it is not an issue. I think... After booting to linux I can see similar error message in dmesg, but now raw ID is correct: It looks like: unknown raw ID 0x002c142c Here flash ID is correct... But still unknown... But I can't provide excel log lines right now. Purpose is to get a bootable qspi-flash, but I'm still completely stuck... Thank you in advance Looking forward for you reply вт, 25 ма�? 2021 г. в 18:47, ST Community :

[PatrickF]

Hi,

maybe try putting

bias-pull-up;

for data lanes too (if not present on your PCB) instead of 'bias-disable;'

Regards.

[ASkri.1]

I will try... But't according to AN5031 external pullups is not required for data lines, except CS pin Please refer to Figure 39 Anyway I will try and send feedback to you ASAP. Thank you very much �?р, 26 ма�? 2021 г. в 19:40, ST Community :

[PatrickF]

AN5031 figure 39 show internal pull-ups, it depend on your design choice, it is either internal or external (sometimes both).

In case of boot from Serial-NAND, BootROM will setup pull-up on IO0 and IO1, but this is later override by DT settings.

I'm not sure it is the root cause (it should work without them), but easy to give it a try.

On our side, MT29F1G01ABAFD12-IT:F has been tested and it work for BootROM without fusing OTP WORD9.

Maybe worth to try with latest Ecosystem v3.0 (recommended for new design).

see also https://wiki.st.com/stm32mpu/wiki/How_to_configure_U-Boot_for_your_board

Maybe provide TSV and complete UART console log during flashing could help too.

[ASkri.1]

Hi, Patrick! Thank you very much for your quick reply. There are following steps performed: 1. Added 10k pull-ups to all IOx, CS and CLK pins of qspi flash; 2. Modified DT. I have added current DT nodes to the end of this letter; 3. All tested again. Here is TSV file generated for SPI nand: #Opt Id Name Type IP Offset Binary - 0x01 fsbl1-boot Binary none 0x0 ../../arm-trusted-firmware/tf-a-stm32mp157a-stm32mp151-dk1-mx-serialboot.stm32 - 0x03 ssbl-boot Binary none 0x0 ../../bootloader/u-boot-stm32mp157a-stm32mp151-dk1-mx-trusted.stm32 P 0x04 fsbl1 Binary(2) nand0 0x00000000 ../../arm-trusted-firmware/tf-a-stm32mp157a-stm32mp151-dk1-mx-trusted.stm32 P 0x06 ssbl Binary nand0 0x00200000 ../../bootloader/u-boot-stm32mp157a-stm32mp151-dk1-mx-trusted.stm32 P 0x07 ssbl2 Binary nand0 0x00400000 ../../bootloader/u-boot-stm32mp157a-stm32mp151-dk1-mx-trusted.stm32 P 0x21 ubifs System nand0 0x00600000 ../../st-image-weston-openstlinux-weston-stm32mp1-disco-mx_nand_4_256_multivolume.ubi Here is console output I'm trying to load it to board: U-Boot 2020.01-stm32mp-r1 (Jan 06 2020 - 20:56:31 +0000) CPU: STM32MP157DAB Rev.Z Model: STMicroelectronics STM32MP157A-DK1 STM32CubeMX board Board: stm32mp1 in trusted mode (st,stm32mp157a-stm32mp151-dk1-mx) DRAM: 512 MiB Clocks: - MPU : 800 MHz - MCU : 208.878 MHz - AXI : 266.500 MHz - PER : 24 MHz - DDR : 533 MHz WDT: Started with servicing (32s timeout) *NAND: 0 MiB*MMC: STM32 SD/MMC: 0 In: serial Out: serial Err: serial invalid MAC address in OTP 00:00:00:00:00:00 stm32 vrefbuf timed out: -110 adc@0: can't enable vdd-supply!board_check_usb_power: single shot failed for adc@0[18]! Net: Error: ethernet@5800a000 address not set. No ethernet found. Hit any key to stop autoboot: 0 Boot over usb0! *unknown raw ID d7f41ba8Error: MTD device nand0 not found*DFU alt info setting: done crq->brequest:0x0 Reset requested # UPLOAD ... done Ctrl+C to exit ... If I continue to load linux kernel from eMMC connected, I'm getting following dmesg messages related to nand: root@stm32mp1-disco-mx:~# dmesg | grep spi [ 2.658599] spi-nand spi0.0: unknown raw ID ff*2c14*2c [ 2.662127] spi-nand: probe of spi0.0 failed with error -524 2�?14 here is the correct flash_id. But I don't know ff before and 2c again after... Also have no Ideas why :) SPI speed is 4Mhz only to avoid possible hardware problems. Here is DT nodes related to qspi: TF-A: quadspi_pins_mx: quadspi_mx-0 { pins1 { pinmux = , /* QUADSPI_BK1_NCS */ , /* QUADSPI_BK1_IO3 */ , /* QUADSPI_BK1_IO2 */ , /* QUADSPI_BK1_IO0 */ ; /* QUADSPI_BK1_IO1 */ // bias-disable; bias-pull-up; drive-push-pull; slew-rate = <1>; }; pins2 { pinmux = ; /* QUADSPI_CLK */ bias-pull-up; // bias-disable; drive-push-pull; slew-rate = <2>; }; }; &qspi { pinctrl-names = "default"; pinctrl-0 = <&quadspi_pins_mx>; reg = <0x58003000 0x1000>, <0x70000000 0x8000000>; #address-cells = <1>; #size-cells = <0>; status = "okay"; nand0: mt29f1g01abafd@0 { compatible = "spi-nand"; reg = <0>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; spi-max-frequency = <4000000>; #address-cells = <1>; #size-cells = <1>; }; }; u-boot & linux: quadspi_pins_mx: quadspi_mx-0 { u-boot,dm-pre-reloc; pins1 { u-boot,dm-pre-reloc; pinmux = , /* QUADSPI_BK1_NCS */ , /* QUADSPI_BK1_IO3 */ , /* QUADSPI_BK1_IO2 */ , /* QUADSPI_BK1_IO0 */ ; /* QUADSPI_BK1_IO1 */ // bias-disable; bias-pull-up; drive-push-pull; slew-rate = <1>; }; pins2 { u-boot,dm-pre-reloc; pinmux = ; /* QUADSPI_CLK */ // bias-disable; bias-pull-up; drive-push-pull; slew-rate = <2>; }; }; quadspi_sleep_pins_mx: quadspi_sleep_mx-0 { u-boot,dm-pre-reloc; pins { u-boot,dm-pre-reloc; pinmux = , /* QUADSPI_BK1_NCS */ , /* QUADSPI_BK1_IO3 */ , /* QUADSPI_BK1_IO2 */ , /* QUADSPI_BK1_IO0 */ , /* QUADSPI_BK1_IO1 */ ; /* QUADSPI_CLK */ }; }; &qspi { u-boot,dm-pre-reloc; pinctrl-names = "default", "sleep"; pinctrl-0 = <&quadspi_pins_mx>; pinctrl-1 = <&quadspi_sleep_pins_mx>; reg = <0x58003000 0x1000>, <0x70000000 0x8000000>; #address-cells = <1>; #size-cells = <0>; status = "okay"; nand0: mt29f1g01abafd@0 { u-boot,dm-pre-reloc; compatible = "spi-nand"; reg = <0>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; spi-max-frequency = <4000000>; #address-cells = <1>; #size-cells = <1>; }; }; qspi clock is enabled in &rcc_node for both TF-A and U-BOOT: st,pkcs = < CLK_CKPER_HSE // CLK_ETH_PLL4P * CLK_QSPI_ACLK* CLK_ETH_DISABLED CLK_SDMMC12_PLL4P Distribution package is: openstlinux-5.4-dunfell-mp1-20-06-24 Should I compile u-boot myself? :) Thank you in advance Looking forward for your repl чт, 27 ма�? 2021 г. в 09:31, ST Community :