Hi,
I am working on STM32MP133FAFx . I have integrated PMIC and getting 1.35V voltage to DDR.
I am using bare-metal environment without OS
Also configured required registers for DDR with below values for my hardware,
DDR_MSTR 0x00040401
DDR_MRCTRL0 0x00000010
DDR_MRCTRL1 0x00000000
DDR_DERATEEN 0x00000000
DDR_DERATEINT 0x00800000
DDR_PWRCTL 0x00000000
DDR_PWRTMG 0x00400010
DDR_HWLPCTL 0x00000000
DDR_RFSHCTL0 0x00210000
DDR_RFSHCTL3 0x00000000
DDR_RFSHTMG 0x0075007D
DDR_CRCPARCTL0 0x00000000
DDR_DRAMTMG0 0x12182012
DDR_DRAMTMG1 0x000A041A
DDR_DRAMTMG2 0x0608090F
DDR_DRAMTMG3 0x0050400C
DDR_DRAMTMG4 0x08040508
DDR_DRAMTMG5 0x05050403
DDR_DRAMTMG6 0x02020002
DDR_DRAMTMG7 0x00000202
DDR_DRAMTMG8 0x00001005
DDR_DRAMTMG14 0x000000A0
DDR_ZQCTL0 0xC2000040
DDR_DFITMG0 0x02060105
DDR_DFITMG1 0x00000202
DDR_DFILPCFG0 0x07000000
DDR_DFIUPD0 0xC0400003
DDR_DFIUPD1 0x00000000
DDR_DFIUPD2 0x00000000
DDR_DFIPHYMSTR 0x00000000
DDR_ADDRMAP1 0x00080808
DDR_ADDRMAP2 0x00000000
DDR_ADDRMAP3 0x00000000
DDR_ADDRMAP4 0x00001F1F
DDR_ADDRMAP5 0x07070707
DDR_ADDRMAP6 0x0F0F0707
DDR_ADDRMAP9 0x00000000
DDR_ADDRMAP10 0x00000000
DDR_ADDRMAP11 0x00000000
DDR_ODTCFG 0x06000600
DDR_ODTMAP 0x00000001
DDR_SCHED 0x00000F01
DDR_SCHED1 0x00000000
DDR_PERFHPR1 0x00000001
DDR_PERFLPR1 0x04000200
DDR_PERFWR1 0x08000400
DDR_DBG0 0x00000000
DDR_DBG1 0x00000000
DDR_DBGCMD 0x00000000
DDR_POISONCFG 0x00000000
DDR_PCCFG 0x00000010
DDR_PCFGR_0 0x00000000
DDR_PCFGW_0 0x00000000
DDR_PCFGQOS0_0 0x00100009
DDR_PCFGQOS1_0 0x00000020
DDR_PCFGWQOS0_0 0x01100B03
DDR_PCFGWQOS1_0 0x01000200
DDR_PGCR 0x01442E02
DDR_PTR0 0x00226698
DDR_PTR1 0x0413A980
DDR_PTR2 0x042D7700
DDR_ACIOCR 0x10400812
DDR_DXCCR 0x00000C40
DDR_DSGCR 0xF200011F
DDR_DCR 0x0000000B
DDR_DTPR0 0x34B288D0
DDR_DTPR1 0x097D00C0
DDR_DTPR2 0x10023200
DDR_MR0 0x00000840
DDR_MR1 0x00000000
DDR_MR2 0x00000208
DDR_MR3 0x00000000
DDR_ODTCR 0x00010000
DDR_ZQ0CR1 0x00000038
DDR_DX0GCR 0x0000CE81
DDR_DX1GCR 0x0000CE81
Also used below steps to configure
1. RESETS: presetn, core_ddrc_rstn, aresetn
2. Enable clock
3. Deassert reset
4. Delay
5. Initialize registers
6. Deassert reset signal core_ddrc_rstn, aresetn and presetn
7. Start PHY init by accessing relevant PUBL registers
8. Monitor PHY init status by polling PUBL register PGSR.IDONE
9. Indicate to PUBL that controller performs SDRAM initialization
10.SET DFIMISC INIT Complete flag to 1
11. Wait for DWC_ddr_umctl2 to move to normal operation mode
12. Disable Auto refresh and power down
12. Program PUBL PGCR to enable refresh during training and rank to train
14. Configure PUBL PIR register to run training step
15. Monitor PUB PGSR.IDONE to poll completion of training sequence
16. Enable auto refresh
But I am not able to access the DDR memory which is from 0xC0000000. When I am trying to access memory, processor is behaving abnormal
Please help me how to resolve this issue and provide me the solution.
