Memory equalization - How are the traces measured?

[DMårt]

I downloaded the STM32MP151AAC3 example model (.zip file) that routes traces to the DDR3L memory

STM32MP151A - MPU with Arm Cortex-A7 650 MHz, Arm Cortex-M4 real-time coprocessor, TFT display - STMicroelectronics

Then I measured DDR_Q1 to DDR_7, DQM0, DQS0_P and DQS0_N and filled the Excel table that is included inside the downloaded .zip file.

Here is the result:

I have been using Altium CircuitMaker (very similar to Altium Designer).

I measured by first pressing CTRL+H and then mark one part of the track and then I press this button.

But when I look at the Excel spred sheet that ST have made, they show me these numbers.

My question is: What are ST doing to getting the length of DQ0, DQ1, DQ5 and DQ6 ? It seems that they are the only ones that differs. Others seems to be similar. 

If they are changed in the model, but not in the Excel spred sheet, which values should I follow? The values made by ST, or the hard ware example model made by ST?

The reason why I'm asking this question is becuse the minimal clearance in the BGA for the DDR3L tracks, is 0.08mm. I need to re-route some tracks to increase the minimal electrical clearance.

[PatrickF]

Hi @DMårt 

checked the STM32MP15XXAC_1DDR3L. For me it is OK.

DDR_CLK_N reported by Altium Designer to have a total length of 49.769mm (This includes the 2 x vias for 1.534 each).

Type	Layer	Length (mm)
Track	Top Layer	1.875
Track	Top Layer	0.566
Track	Bottom Layer	0.175
Track	Bottom Layer	0.248
Track	Bottom Layer	1.22
Track	Bottom Layer	0.509
Track	Bottom Layer	0.17
Track	Bottom Layer	0.099
Track	Bottom Layer	0.409
Track	Bottom Layer	0.17
Track	Bottom Layer	0.128
Track	Bottom Layer	4.025
Track	Bottom Layer	0.459
Track	Bottom Layer	0.17
Track	Bottom Layer	0.17
Track	Bottom Layer	3.975
Track	Bottom Layer	7.224
Track	Bottom Layer	5.45
Track	Bottom Layer	5.5
Track	Bottom Layer	0.403
Track	Bottom Layer	0.396
Track	Bottom Layer	0.39
Track	Bottom Layer	0.424
Track	Bottom Layer	0.424
Track	Bottom Layer	0.525
Track	Bottom Layer	0.53
Track	Bottom Layer	6.25
Track	Bottom Layer	0.849
Track	Bottom Layer	0.275
Track	Top Layer	0.566
Track	Bottom Layer	0.283
Track	Bottom Layer	0
Track	Bottom Layer	0.106
Track	Bottom Layer	0.304
Track	Bottom Layer	0.495
Track	Bottom Layer	0.976
Track	Bottom Layer	0.435
Track	Bottom Layer	0.453
Track	Bottom Layer	0.075
Via	MultiLayer	1.534
Via	MultiLayer	1.534

The wire going to the 100 ohms is reported to be 2.738mm long (values in red above)

so, final DDR_CLK_N length is : 49.769 - 2.738 = 47.03mm, which is the value in the excel

I think you accounted the 2 x vias twice.

Regards,

[DMårt]

@PatrickF 

Hmm. I don't have any Altium Designer licence. Only Altium CircuitMaker. It's a freeware version of Designer, very similar.

It must happen something when I exported the model from my trail Altium Designer to Altium CircuitMaker. 

Anyway! I hade to re-route everything because I found two critical things:

1. The minimal electrical clearance was 0.08mm between track to track
2. The minimal eletrical clearance was 0.08mm between pad edge to track

I changed that to 0.1mm but with one exception of BGA pad, there I configure the DRC rule to 0.09mm between pad to track because JLCPCB can only produce with a minimum 0.1mm electical clearance, with an exception to BGA pads. JLCPCB will cut the edge of the pad if a track of 0.09mm in width passing through a BGA with pitch of 0.5mm.

One major difference I made is to change this. This is a print screen from Altium 365.

To this. This is a print screen from Altium CircuitMaker.

That resulted: 

The Byte0 has only a minor change. But byte1 has a major change. Also the track width is 0.09mm due to the impedance.

One more difference is this. The upper is mine. The lower is from ST.

I don't like to be close to the limit.

Anyway. Feel free to open the model in Altium365: STM32 Computer | Projects | CircuitMaker

And the address.

[PatrickF]

Thanks for the details and the rationale.

We have seen the DDR3L quite robust with STM32MP1, even more with terminations (optional in x16). Only failing when routing was completely mistaken.

Regards.