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LSE crystal for ST32MP1 - FC 135 38.768 kHz

DMårt
Lead

Hi!

I noticed this.

The FC-135 32.768 kHz crystall with CL = 12.5 pF, ESR max = 70 kOhm and C0 = 1.0 pF is suitable for MP1 products.

The gmcrit is 2.1631 uA/V.

When I do the math, i found out that gain margin is below 5.

C0 = 1.0*10^-12;
CL = 12.5*10^-12;
ESR = 70*10^3;
F = 32.768*10^3;
Cs = 7*10^-12; % Assume that stray capacitance is 7 pF
gm = 8.5*10^-6;

% Gain margins critical
gm_crit = 4*ESR*(2*pi*F)^2*(C0 + CL)^2
gain_margin = gm/gm_crit

% Capacitors
C = (2*CL - 2*Cs)*10^12

 

Output:

gm_crit = 2.1631e-06
gain_margin = 3.9295
C = 11.0000

 

Skärmbild 2024-05-26 124129.png

 

Because the gm value of 8.5 can be found here

Skärmbild 2024-05-26 124604.png

 

Why does ST recommend FC-135 32.768 kHz when the gm_crit_max is below the gm_crit value?

Skärmbild 2024-05-26 124754.png

STM32MP151AAC3 custom board with STM32-OS as operating system: https://github.com/DanielMartensson/STM32-Computer
5 REPLIES 5
STOne-32
ST Employee

Dear @DMårt ,

Thank you for the valuable post, indeed the whole line is applicable to all 4 software drive levels from low to high .

IMG_8233.jpeg

 in case of 12,5pF CL crystal,using High drive is a MUST . So Gm using that mode becomes 13,5 and not 8,5 which is for Medium High level .

Hope it helps you .

STOne-32

@STOne-32 

Thank you. Now I understand!

Do you think 10pF capacitors will work?

STM32MP151AAC3 custom board with STM32-OS as operating system: https://github.com/DanielMartensson/STM32-Computer

Hi @DMårt ,

Cs are in general between 2 to 3 pF with a good optimized PCB layout . CL1 and CL2 capacitors would be about 12,5pF - 3pF = 9,5pF * 2 so in range of 18pF in this case .

if Cs = 5,5pF ( worst case ) , CL1 and CL2 would be in range of 14pF . All of these calculations are based on A Crystal load of 12,5 pF to oscillate as close as possible to 32,768Khz frequency and have a low PPM drift vs Nominal frequency.

Hope it helps ,

STOne-32

PatrickF
ST Employee

HI @DMårt 

in fact the Gmcritmax in product datasheets already take the x5 margin into account.

Nevertheless, from my side, although 12.5pF will work with high-drive, I recommend to chose a crystal with CL around 6pF which allows to use default medium-high drive. Drawback of low CL could be higher pullability, which mean PCB load capacitors might need be adapted with real Cs if good LSE accuracy (<100ppm) is a must.

It seems the trend is to have smaller crystals with slightly lower CL value as mainstream (i.e. good availability and quantity pricing).

Regards.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.

@PatrickF 

Thank you for your reply.

I think I will choose the Epson FC 135 LSE crystal due to the availability at the manufacturer JLCPCBs stock.

Q13FC13500004 | Seiko Epson | Crystals | JLCPCB

 

My goal is to produce an STM32MP board for a minium price. It's going to be open source as well.

STM32MP151AAC3 custom board with STM32-OS as operating system: https://github.com/DanielMartensson/STM32-Computer