Is byte lane swapping in 16x bit DDR3 RAM possible?

[FWebe.3]

Hello,

I read the AN5122 which explains in chapter 4.2, that the RAM lane byte 0 must be connected to byte 0 of the MP1 and that the bits swapping is not possible.

However on the EV1 board, the bits inside byte 0 lane are swapped. Furthermore, i do not know how to identify byte 0 at the ram chip, since i want to use two of them.

For the design I am working on, I need 1GB DDR3L RAM, split in two 512MB RAM chips. In the AN I found this picture:

I'd like to place the two chips next to each other, using STM32MP1's Byte 2 / Byte 0 for chip 1 and Byte 1 / Byte 3 for chip 2.

Is this possible to do?

Thanks

[PatrickF · Accepted solution]

Hi,

AN5122 section 4 is for LPDDR2 or LPDDR3.

For DDR3 and DDR3L, please look at section 3.

I confirm that for DDR3 or DDR3L, as stated in AN5122, byte swap is allowed as well as bit swap within a byte.

Regards.

[Alex - APMemory]

Hi 

by the way, if any PCB limitation, you can also use 1GB DDR3 in single package instead  of 2pces of 512MB DDR3 like A3T8GF43BBF (we have tested it on STM32MP135F)

Alex