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Enable HS200/HS400 mode of eMMC in STM32MP157F-eval board

Pratik Manvar
Associate II

Hi STM-Team,

We are trying to enable/configure HS200/HS400 mode in eMMC on STM32MP157F-EV1 evaluation board.

We are using the stm32mp157f-ev1.dts device tree and we have configured the eMMC node as shown in below screenshot.

0693W00000Unj0nQAB.png 

As per the documentation, we came to know that to select HS200/HS200/HS400, VCCQ has to be set to 1.8 V or 1.2 V.

So, we have set "vqmmc-supply" property in device tree to 1.8 range regulator i.e. "v1v8" as shown below.

------------------------------------------------------------------------

v1v8: ldo6 {

                regulator-name = "v1v8";

                regulator-min-microvolt = <1800000>;

                regulator-max-microvolt = <1800000>;

                interrupts = <IT_CURLIM_LDO6 0>;

        };

------------------------------------------------------------------------

For the above changes, we are facing the below errors.

------------------------------------------------------------------------

root@stm32mp1:~# dmesg | grep -i mmc

[  3.601403] mmci-pl18x 58005000.sdmmc: mmc0: PL180 manf 53 rev2 at 0x58005000 irq 50,0 (pio)

[  3.638210] mmci-pl18x 58007000.sdmmc: mmc1: PL180 manf 53 rev2 at 0x58007000 irq 51,0 (pio)

[  3.650613] mmci-pl18x 58007000.sdmmc: Voltage switch failed

[  3.762958] mmc0: new ultra high speed SDR104 SDHC card at address aaaa

[  3.778533] mmcblk0: mmc0:aaaa SD32G 29.7 GiB 

[  3.828382] mmcblk0: p1 p2 p3 p4 p5 p6 p7

[  3.848015] mmci-pl18x 58007000.sdmmc: Voltage switch failed

[  3.853624] mmc1: error -110 whilst initialising MMC card

[  3.874264] mmci-pl18x 58007000.sdmmc: Voltage switch failed

[  4.091082] mmc1: error -110 whilst initialising MMC card

[  4.284590] mmci-pl18x 58007000.sdmmc: Voltage switch failed

[  4.518407] mmc1: error -110 whilst initialising MMC card

-----------------------------------------------------------------------------------------------------

Is there anything we are missing out to configure the HS200/HS400 mode for eMMC. 

It would be great help to us for this issue.

Thanks,

Pratik Manvar

1 ACCEPTED SOLUTION

Accepted Solutions
PatrickF
ST Employee

Hi @Pratik Manvar​ 

On STM32MP15 series, There is no dedicated supply rail for eMMC IOs, so you can't do HS200 without changing the whole VDD IOs to 1.8V.

Furthermore, HS200 has some limitations and you should stick to eMMC high-Speed DDR (up to 104MBytes/s) which works at 3.3V.

See also https://community.st.com/s/question/0D53W00001oHgkbSAC/what-is-the-maximum-data-rate-of-emmc-can-have-with-stm32mp15

Regards,

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4 REPLIES 4
PatrickF
ST Employee

Hi @Pratik Manvar​ 

On STM32MP15 series, There is no dedicated supply rail for eMMC IOs, so you can't do HS200 without changing the whole VDD IOs to 1.8V.

Furthermore, HS200 has some limitations and you should stick to eMMC high-Speed DDR (up to 104MBytes/s) which works at 3.3V.

See also https://community.st.com/s/question/0D53W00001oHgkbSAC/what-is-the-maximum-data-rate-of-emmc-can-have-with-stm32mp15

Regards,

In order to give better visibility on the answered topics, please click on 'Select as Best' on the reply which solved your issue or answered your question. See also 'Best Answers'

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.

Hi @PatrickF​,

Thanks for your quick reply.

Yes, we understand the limitation to set HS200 mode of eMMC in STM32MP15 series platform.

We are able to set High-Speed as well as DDR52 mode of eMMC (please see below snaps).

0693W00000UnnjIQAR.png0693W00000UnnkQQAR.pngIn both the cases, the clock is 52MHz and we can measure the same write throughput using dd command.

Can you please help us to understand, what is the practical read/write speed for High-Speed and DDR52 modes of eMMC?

Thanks,

Pratik Manvar

Hi @Pratik Manvar​ 

I can only state for raw bandwidth.

See Table "SDMMC operation modes e•MMC" in STM32MP15 Reference Manual.

I guess the 'High-speed' you got is SDR, so 49.5MBytes/s raw bandwidth (as real clock is 49.5MHz).

The DDR52 is then going twice as fast, so 99MBytes/s raw bandwidth.

The real throughput depend on the memory performances with the block size used by Linux (most of the time not really clear from part eMMC datasheets) and as well by the Linux driver efficiency.

The THGBMBG5D1KBAIT on STM32MP157F-EV1 is stated for DDR52 at 88MB/s read and 12MB/s write. This is maybe not achieved on a real platform due to some SW overhead.

Regards.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.

Thanks for the clarity @PatrickF​.

B. Regards,

Pratik Manvar