2021-11-03 11:47 AM
Hi,
We are using the STM32MP157f-ev1 board for our initial development and this is our first time using Linux kernel, we have been following the development package wiki links for building kernel, u-boot and tf-a. We used the STM32CubeIDE's inbuilt cubeMx to generate device trees.
For now we have been successful with modifying the kernel device tree to enable couple of USARTs, build it in kernel code base, push it to target, modify the mmc0_extlinux/stm32mp157f-ev1_extlinux.conf in boot partition to load the custom device tree while booting up, test them on the evaluation board and the USARTs are working as expected and we see successful data transfers.
However when we modify the clock configuration using the STMCubeIDE/CubeMx we see the changes are being done to the device tree under u-boot and tf-a folders.
I have the following questions:
Any help is much appreciated.
Thanks.
Solved! Go to Solution.
2021-11-08 11:27 PM
Hi,
Cortex-A7 frequency is managed slightly differently by default, using an opp table with one or two points, please have a look to:
https://wiki.st.com/stm32mpu/wiki/How_to_change_the_CPU_frequency
In that default case, PLL1 settings are not required.
Regards.
2021-11-04 02:59 AM
Hi,
maybe this link could help you to understand DT hierarchy which is not exactly the same for the provided Starter Package and CubeMx generated.
https://wiki.st.com/stm32mpu/wiki/STM32MP15_device_tree#STM32CubeMX_generated_device_tree
for point 1, I'm not expert, but I understand that for TF-A and u-Boot, the DTS is included in the binary (of within FIP for u-Boot)
https://wiki.st.com/stm32mpu/wiki/How_to_compile_the_device_tree_with_the_Developer_Package
For point 2, I cannot answer, but this might be solved by includes.
Regards.
2021-11-08 11:02 AM
Hi Patrick,
Thanks for the reponse.
I followed few other wiki links and was able to build custom tf-a and u-boot and load them on to the STM32MP157f-ev1 board. I see my clock changes for peripherals and MCU are being set properly except for the MPU clock.
For some reason even though the device tree has the custom PLL1 clock configurations for the MPU, it is not reflected when I see the /sys/kernel/debug/clk/clk_summary.
Is there any restrictions on modifying MPU clock?
Is there any other settings/permissions/flags to be enabled inorder to modify ther MPU clock?
Thanks,
Shalini
2021-11-08 11:27 PM
Hi,
Cortex-A7 frequency is managed slightly differently by default, using an opp table with one or two points, please have a look to:
https://wiki.st.com/stm32mpu/wiki/How_to_change_the_CPU_frequency
In that default case, PLL1 settings are not required.
Regards.
2021-11-11 06:11 PM
Hi Patrick,
Thanks for sharing the link. I observed that even if I set the pll1:st,pll@0 in the tf-a device tree with dividers/multiplier to generate to 650MHz, when the kernel boots up it is changed to 800MHz of 400MHz based on the load and these values are taken from the opp table (stm32mp15xd.dtsi for my eval board).
Looks like the opp table always overrides the clock settings in device tree. So for now I skipped modifying the device tree for MPU clock and set them in opp table instead.
Thanks,
Shalini
2021-11-12 12:07 AM
Hi @SKris ,
your understanding is correct, the OPP table override the PLL1 manual setting.
Regards.
In order to give better visibility on the answered topics, please click on 'Select as Best' on the reply which solved your issue or answered your question. See also 'Best Answers'