2021-03-31 04:26 PM
I'm DDR tuning a custom STM32MP157F board with 4GB DDR3. All DDR tests are passing however I get the following tuning failure for Bit Deskew: Failed [Cannot Deskew lines, there is no PASS region] and Eye Training: [Cannot DQS timings, there is no PASS region]
What exactly does this mean? How can it fail tuning but pass testing?
DDR>test 0
...
loop 1: 0/17 test failed
Result: Pass [loop 1: 17 tests passed]
DDR>tuning 1
execute 1:Bit de-skew
Result: Failed [Cannot Deskew lines, there is no PASS region]
Result: Failed [Cannot Deskew lines, there is no PASS region]
Result: Failed [error = 2]
DDR>tuning 2
execute 2:Eye Training
Result: Failed [Cannot DQS timings, there is no PASS region]
Byte 1, DQS unit = 3, phase = 3
Result: Failed [error = 1]
DDR>tuning 3
execute 3:Display registers
Byte 0 Dekew result, bit0 delay, bit1 delay...bit8 delay
2 2 2 2 2 2 2 2
dxndllcr: [5a0041cc] val:400a0000
dxnqdstr: [5a0041d4] val:3db02001
dxndqtr: [5a0041d0] val:aaaaaaaa
Byte 1 Dekew result, bit0 delay, bit1 delay...bit8 delay
2 2 2 2 2 2 2 2
dxndllcr: [5a00420c] val:40000000
dxnqdstr: [5a004214] val:3db02001
dxndqtr: [5a004210] val:aaaaaaaa
Result: Pass []
DDR>tuning 4
execute 4:Bist config
Bist.nbErr = 1
Bist.Seed = 0x1234abcd
Result: Pass []
Solved! Go to Solution.
2021-04-02 10:47 AM
Hello TStru.1 (Community Member)
An issue has been identified regarding DQS Gating (function call missing) and will be corrected in next release of CubeMx/DDR tool (v6.3)
You still can run DDR tool and apply the calibration values from the test, but you'll need to update 4 registers manually if you want to include the DQS values in the DT.
https://wiki.st.com/stm32mpu/wiki/DDRCTRL_and_DDRPHYC_device_tree_configuration
In my case (16-bit DDR)
DDR>step 3
current step is 3:DDR_READY
DDR>tuning 0
execute 0:Read DQS gating
Byte 0, R0DGSL = 2, R0DGPS = 0
Byte 1, R0DGSL = 2, R0DGPS = 0
Result: Pass []
-> According to the DQS gating above and the corresponding table (shown below), I need to update manually DX0DQSTR, DX1DQSTR as follow
DX0DQSTR 0x3DB00002
DX1DQSTR 0x3DB00002
For a 32-bit DDR (in your case) you will have also Byte2, Byte3 showing values.
update manually the 4 registers : DX0DQSTR/DX1DQSTR/DX2DQSTR/DX3DQSTR
Here's the corresponding table to update the registers according to DQS values:
Example for Byte 0 with all combinations from DQS Gating,
( same table for Byte1 = DX1DQSTR, Byte2 = DX2DQSTR, Byte3 =DX3DQSTR)
Byte 0, R0DGSL = 0, R0DGPS = 0 => DX0DQSTR = 0x3DB00000
Byte 0, R0DGSL = 0, R0DGPS = 1 => DX0DQSTR = 0x3DB01000
Byte 0, R0DGSL = 0, R0DGPS = 2 => DX0DQSTR = 0x3DB02000
Byte 0, R0DGSL = 0, R0DGPS = 3 => DX0DQSTR = 0x3DB03000
Byte 0, R0DGSL = 1, R0DGPS = 0 => DX0DQSTR = 0x3DB00001
Byte 0, R0DGSL = 1, R0DGPS = 1 => DX0DQSTR = 0x3DB01001
Byte 0, R0DGSL = 1, R0DGPS = 2 => DX0DQSTR = 0x3DB02001
Byte 0, R0DGSL = 1, R0DGPS = 3 => DX0DQSTR = 0x3DB03001
Byte 0, R0DGSL = 2, R0DGPS = 0 => DX0DQSTR = 0x3DB00002
Byte 0, R0DGSL = 2, R0DGPS = 1 => DX0DQSTR = 0x3DB01002
Byte 0, R0DGSL = 2, R0DGPS = 2 => DX0DQSTR = 0x3DB02002
Byte 0, R0DGSL = 2, R0DGPS = 3 => DX0DQSTR = 0x3DB03002
Byte 0, R0DGSL = 3, R0DGPS = 0 => DX0DQSTR = 0x3DB00003
Byte 0, R0DGSL = 3, R0DGPS = 1 => DX0DQSTR = 0x3DB01003
Byte 0, R0DGSL = 3, R0DGPS = 2 => DX0DQSTR = 0x3DB02003
Byte 0, R0DGSL = 3, R0DGPS = 3 => DX0DQSTR = 0x3DB03003
Byte 0, R0DGSL = 4, R0DGPS = 0 => DX0DQSTR = 0x3DB00004
Byte 0, R0DGSL = 4, R0DGPS = 1 => DX0DQSTR = 0x3DB01004
Byte 0, R0DGSL = 4, R0DGPS = 2 => DX0DQSTR = 0x3DB02004
Byte 0, R0DGSL = 4, R0DGPS = 3 => DX0DQSTR = 0x3DB03004
Byte 0, R0DGSL = 5, R0DGPS = 0 => DX0DQSTR = 0x3DB00005
Byte 0, R0DGSL = 5, R0DGPS = 1 => DX0DQSTR = 0x3DB01005
Byte 0, R0DGSL = 5, R0DGPS = 2 => DX0DQSTR = 0x3DB02005
Byte 0, R0DGSL = 5, R0DGPS = 3 => DX0DQSTR = 0x3DB03005
Byte 0, R0DGSL = 6, R0DGPS = 0 => DX0DQSTR = 0x3DB00006
Byte 0, R0DGSL = 6, R0DGPS = 1 => DX0DQSTR = 0x3DB01006
Byte 0, R0DGSL = 6, R0DGPS = 2 => DX0DQSTR = 0x3DB02006
Byte 0, R0DGSL = 6, R0DGPS = 3 => DX0DQSTR = 0x3DB03006
Byte 0, R0DGSL = 7, R0DGPS = 0 => DX0DQSTR = 0x3DB00007
Byte 0, R0DGSL = 7, R0DGPS = 1 => DX0DQSTR = 0x3DB01007
Byte 0, R0DGSL = 7, R0DGPS = 2 => DX0DQSTR = 0x3DB02007
Byte 0, R0DGSL = 7, R0DGPS = 3 => DX0DQSTR = 0x3DB03007
2021-04-02 10:47 AM
Hello TStru.1 (Community Member)
An issue has been identified regarding DQS Gating (function call missing) and will be corrected in next release of CubeMx/DDR tool (v6.3)
You still can run DDR tool and apply the calibration values from the test, but you'll need to update 4 registers manually if you want to include the DQS values in the DT.
https://wiki.st.com/stm32mpu/wiki/DDRCTRL_and_DDRPHYC_device_tree_configuration
In my case (16-bit DDR)
DDR>step 3
current step is 3:DDR_READY
DDR>tuning 0
execute 0:Read DQS gating
Byte 0, R0DGSL = 2, R0DGPS = 0
Byte 1, R0DGSL = 2, R0DGPS = 0
Result: Pass []
-> According to the DQS gating above and the corresponding table (shown below), I need to update manually DX0DQSTR, DX1DQSTR as follow
DX0DQSTR 0x3DB00002
DX1DQSTR 0x3DB00002
For a 32-bit DDR (in your case) you will have also Byte2, Byte3 showing values.
update manually the 4 registers : DX0DQSTR/DX1DQSTR/DX2DQSTR/DX3DQSTR
Here's the corresponding table to update the registers according to DQS values:
Example for Byte 0 with all combinations from DQS Gating,
( same table for Byte1 = DX1DQSTR, Byte2 = DX2DQSTR, Byte3 =DX3DQSTR)
Byte 0, R0DGSL = 0, R0DGPS = 0 => DX0DQSTR = 0x3DB00000
Byte 0, R0DGSL = 0, R0DGPS = 1 => DX0DQSTR = 0x3DB01000
Byte 0, R0DGSL = 0, R0DGPS = 2 => DX0DQSTR = 0x3DB02000
Byte 0, R0DGSL = 0, R0DGPS = 3 => DX0DQSTR = 0x3DB03000
Byte 0, R0DGSL = 1, R0DGPS = 0 => DX0DQSTR = 0x3DB00001
Byte 0, R0DGSL = 1, R0DGPS = 1 => DX0DQSTR = 0x3DB01001
Byte 0, R0DGSL = 1, R0DGPS = 2 => DX0DQSTR = 0x3DB02001
Byte 0, R0DGSL = 1, R0DGPS = 3 => DX0DQSTR = 0x3DB03001
Byte 0, R0DGSL = 2, R0DGPS = 0 => DX0DQSTR = 0x3DB00002
Byte 0, R0DGSL = 2, R0DGPS = 1 => DX0DQSTR = 0x3DB01002
Byte 0, R0DGSL = 2, R0DGPS = 2 => DX0DQSTR = 0x3DB02002
Byte 0, R0DGSL = 2, R0DGPS = 3 => DX0DQSTR = 0x3DB03002
Byte 0, R0DGSL = 3, R0DGPS = 0 => DX0DQSTR = 0x3DB00003
Byte 0, R0DGSL = 3, R0DGPS = 1 => DX0DQSTR = 0x3DB01003
Byte 0, R0DGSL = 3, R0DGPS = 2 => DX0DQSTR = 0x3DB02003
Byte 0, R0DGSL = 3, R0DGPS = 3 => DX0DQSTR = 0x3DB03003
Byte 0, R0DGSL = 4, R0DGPS = 0 => DX0DQSTR = 0x3DB00004
Byte 0, R0DGSL = 4, R0DGPS = 1 => DX0DQSTR = 0x3DB01004
Byte 0, R0DGSL = 4, R0DGPS = 2 => DX0DQSTR = 0x3DB02004
Byte 0, R0DGSL = 4, R0DGPS = 3 => DX0DQSTR = 0x3DB03004
Byte 0, R0DGSL = 5, R0DGPS = 0 => DX0DQSTR = 0x3DB00005
Byte 0, R0DGSL = 5, R0DGPS = 1 => DX0DQSTR = 0x3DB01005
Byte 0, R0DGSL = 5, R0DGPS = 2 => DX0DQSTR = 0x3DB02005
Byte 0, R0DGSL = 5, R0DGPS = 3 => DX0DQSTR = 0x3DB03005
Byte 0, R0DGSL = 6, R0DGPS = 0 => DX0DQSTR = 0x3DB00006
Byte 0, R0DGSL = 6, R0DGPS = 1 => DX0DQSTR = 0x3DB01006
Byte 0, R0DGSL = 6, R0DGPS = 2 => DX0DQSTR = 0x3DB02006
Byte 0, R0DGSL = 6, R0DGPS = 3 => DX0DQSTR = 0x3DB03006
Byte 0, R0DGSL = 7, R0DGPS = 0 => DX0DQSTR = 0x3DB00007
Byte 0, R0DGSL = 7, R0DGPS = 1 => DX0DQSTR = 0x3DB01007
Byte 0, R0DGSL = 7, R0DGPS = 2 => DX0DQSTR = 0x3DB02007
Byte 0, R0DGSL = 7, R0DGPS = 3 => DX0DQSTR = 0x3DB03007