Control LTDC on STM32MP157 by Cortex M4?

MNiko.3 · ‎2020-10-18

Is it possible to control LTDC on STM32MP157 by Cortex M4 co-processor?

I have noticed that there is no available HAL driver for LTDC on STM32MP157.

Why is it so? Can we use the HAL driver for LTDC intended for STM32H7 processors on STM32MP157?

PatrickF · ‎2020-10-19

Hello,

as stated in this page, in our ecosystem deliveries, LTDC is only supported on Cortex-A7 (e.g. Linux) side.

What is the use case to have Cortex-M4 to handle the LTDC ? The frame buffer is usually in DDR, which is also managed by Cortex-A7 side. Would probably be complex to access it concurrently from M4 (and the location of frame buffer in the DDR address range is maybe not fixed when using Linux)

For HW point of view, the LTDC registers are accessible by Cortex-M4, but it is up to you to manage the init (using H7 driver might flight, but I remind not supported/tested on STM32MP1 series).

Accessing Framebuffer in DDR from Cortex-M4 is quite inneficient (due to Cortex-M4 AHB accesses and clock domain crossing) and can impact Cortex-A7 side performances.

If you want to put a small display on Cortex-M4 side, maybe it is worth to look at FMC parallel display or I2C/SPI interfaces. Slower but more independent and using less system resources.

Regards.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.

View solution in original post

PatrickF · ‎2020-10-19

Hello,

as stated in this page, in our ecosystem deliveries, LTDC is only supported on Cortex-A7 (e.g. Linux) side.

What is the use case to have Cortex-M4 to handle the LTDC ? The frame buffer is usually in DDR, which is also managed by Cortex-A7 side. Would probably be complex to access it concurrently from M4 (and the location of frame buffer in the DDR address range is maybe not fixed when using Linux)

For HW point of view, the LTDC registers are accessible by Cortex-M4, but it is up to you to manage the init (using H7 driver might flight, but I remind not supported/tested on STM32MP1 series).

Accessing Framebuffer in DDR from Cortex-M4 is quite inneficient (due to Cortex-M4 AHB accesses and clock domain crossing) and can impact Cortex-A7 side performances.

If you want to put a small display on Cortex-M4 side, maybe it is worth to look at FMC parallel display or I2C/SPI interfaces. Slower but more independent and using less system resources.

Regards.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.

MNiko.3 · ‎2020-10-19

Hello Patrick,

Thank you very much for your fast, precise and complete answer.

We shall move LTDC control on Cortex-A7 side.

Best regards,

Marko Nikolic

PatrickF · ‎2020-10-19

Please click on 'Select as Best' if my reply solved your issue or answered your question.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.