System reset during kernel debug

[mingming]

Using MP135F-DK board.

Setup the environment and rebuild kernel.

After I use openocd and gdb success connect to linux system, try to debug linux kernel, then run some simple gdb command like "bt" or do nothing, then system get reset.

I did not get much useful info from console (minicom).

if I don't pause system and let gdb "continue", then no reset.

Is it because watchdog ? how to disable it.

[mingming]

Hello @PatrickF 

From you answer, seems the document is not correct Datasheet - STM32MP135C STM32MP135F - Arm<Sup>®</Sup> Cortex<Sup>®</Sup>-A7 up to 1 GHz, LCD-TFT, camera interface, 2×ETH, 2×CAN FD, 2×ADC, 24 timers, audio, crypto and adv. security

On document, it say IWDG could be configured as a "free run timer" by option bytes.

By your reply, it's seem like can not configure it as a free run timer. Another point , my understanding from you reply, it's looks like MP135 don't have option bytes. only have OTP, right ?

[PatrickF]

Hi @mingming ,

I agree the datasheet is wrong saying the IWDG could be used as a free running timer as if IWDG is used, its reset action cannot be disabled. This is (badly) inherited from other STM32 products.

On STM32MP products, "option bytes" refer to some OTP which could be tailored by the user to define some low level product 'options' set by the HW during boot sequence.

Regards.

[mingming]

Hi @PatrickF 

Really thanks your info.

Specially, it's One Time Program, means I avoided a mistake 🙂

[mingming]

@PatrickF 

Need your help again. 

I refer to this page GDB - stm32mpu to learn how to write register. it show I need use physic address to access memory. 

 monitor mdw <phys_address> [count] #Display target memory as 32-bit bytes

 Then I download Reference Manual , it show "offset", very sorry that I can not find "base" address of this register.  Normally, which part will mention the "base address of register" ?

I also get some answer from chatgtp, it told me I should use "(gdb) monitor reg w DBGMCU_APB4FZ |= (1 << 2)"

Not sure which one is correct. 

I should try first, then ask. But I'm in office, the device is in home (this is my personal learning), also I'm in Asia.
If I don't ask you now, then I may lost chance to try it at weekend.

Thanks your friendly support.

[PatrickF]

you will find base address information on Reference Manual "Memory map and register boundary addresses"
DBGMCU base address is 0x50081000

Regards.

[mingming]

Hi @PatrickF ,

Try to use gdb command

#for iwdg2, base 0x50081000, offset 2c --> use 0x5008102c

(gdb) monitor mww phys 0x5008102C 0xFFFFFFFF

and for iwdg1, base 0x50081000, offset 4 c --> use 0x5008104c

(gdb) monitor mww phys 0x5008104C 0xFFFFFFFF

But system still get reset.

After  check the detail log, found it's iwdg1 triggered reset.

-------------------------------------------------

NOTICE: CPU: STM32MP135F Rev.Y
NOTICE: Model: STMicroelectronics STM32MP135F-DK Discovery Board
NOTICE: Board: MB1635 Var1.0 Rev.E-02
INFO: PMIC version = 0x21
INFO: Reset reason (0x134):
INFO: IWDG1 Reset (rst_iwdg1)
INFO: FCONF: Reading TB_FW firmware configuration file from: 0x2ffe0000

------------------------------------------

Question: is there some other register to enable DBGMCU feature?

[PatrickF]

Base address for DBGMCU depend on which way the access is done by gdb (I'm not expert of gdb options)

Could your try read back to see if write was successful ?

Base 0x50081000 when access is done thru Cortex-A (debugger could use it), but not working from DAP AXI

Base 0xE0081000 when access is done thru DAP AXI (DDR access when used from Cortex-A)

Maybe try the second one (warning as it could access DDR is not thru DAP AXI).

Regards.