2020-07-22 08:42 AM
Hello,
i'm currently trying to attach a TI DP83848CVV phy to the STM32MP157. We have an external 50MHZ clock which is supplied to the PHY and PA1 (ETH1_REF_CLK).
These are the pinctrl values (generated by CubeMX):
ethernet0_rmii_pins: rmii-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 1, AF11)>, /* ETH1_REF_CLK */
<STM32_PINMUX('B', 12, AF11)>, /* ETH1_TXD0 */
<STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */
<STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */
<STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */
<STM32_PINMUX('C', 5, AF11)>, /* ETH1_RXD1 */
<STM32_PINMUX('G', 12, AF11)>; /* ETH1_PHY_INTN */
bias-disable;
};
pins4 {
pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */
};
};
And the ethernet values:
ðernet0 {
status = "okay";
pinctrl-0 = <ðernet0_rmii_pins>;
pinctrl-names = "default";
phy-mode = "rmii";
phy-handle = <&phy0>;
max-speed = <100>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
};
I'm using the default stm32mp157.dtsi:
ethernet0: ethernet@5800a000 {
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
reg = <0x5800a000 0x2000>;
reg-names = "stmmaceth";
interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<&exti 70 1>;
interrupt-names = "macirq",
"eth_wake_irq",
"stm32_pwr_wakeup";
clock-names = "stmmaceth",
"mac-clk-tx",
"mac-clk-rx",
"ethstp";
clocks = <&rcc ETHMAC>,
<&rcc ETHTX>,
<&rcc ETHRX>,
<&rcc ETHSTP>;
st,syscon = <&syscfg 0x4>;
snps,mixed-burst;
snps,pbl = <2>;
snps,en-tx-lpi-clockgating;
snps,axi-config = <&stmmac_axi_config_0>;
snps,tso;
power-domains = <&pd_core>;
status = "disabled";
};
Under linux, a generic phy gets detected, and phytool also shows us data, but wrong values:
Configuring network interfaces... [ 6.162488] Generic PHY stmmac-0:00: attached PHY driver [Generic PHY] (mii_bus:phy_addr=stmmac-0:00, irq=POLL)
[ 6.183019] dwmac4: Master AXI performs any burst length
[ 6.187173] stm32-dwmac 5800a000.ethernet eth0: No Safety Features support found
[ 6.194290] stm32-dwmac 5800a000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported
[ 6.203155] stm32-dwmac 5800a000.ethernet eth0: registered PTP clock
[ 6.210029] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 7.276918] stm32-dwmac 5800a000.ethernet eth0: Link is Up - 10Mbps/Half - flow control off
[ 7.283904] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
....
root@bytedevkit:~# phytool print eth0/0
ieee-phy: id:0x0000ffff
ieee-phy: reg:BMCR(0x00) val:0000
flags: -reset -loopback -aneg-enable -power-down -isolate -aneg-restart -collision-test
speed: 10-half
ieee-phy: reg:BMSR(0x01) val:0xffff
capabilities: +100-b4 +100-f +100-h +10-f +10-h +100-t2-f +100-t2-h
flags: +ext-status +aneg-complete +remote-fault +aneg-capable +link +jabber +ext-register
The phy id is wrong: 0x0000ffff and should be 0x20005ca0.
Reading any register outputs 0x0000 and 0xfffff alternating.
The TI DP83848CVV driver is built in into the kernel:
root@bytedevkit:~# zcat /proc/config.gz | grep 8384
CONFIG_DP83848_PHY=y
I appreciate any help here, thank you.
2020-07-22 08:59 AM
Hello,
I'm more on the HW side, so I will cover only those aspects.
I understand you are in this situation: https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration#RMII_with_Crystal_on_PHY_-28Reference_clock_-28standard_RMII_clock_name-29_is_provided_by_a_Phy_Crystal-29
Maybe an MDIO bus issue (address, or HW related such as pull-up, voltage, frequency).
2020-07-22 09:06 AM
Hello Patrick,
yes, "3.3.1 RMII with Crystal on PHY (Reference clock (standard RMII clock name) is provided by a Phy Crystal)" is our situation.
I'm checking tomorrow with our HW engineer and will report back.
What do you mean with mdio address? The reg = <0> value in phy0?
Thank you.
Best regards,
Kevin
2020-07-23 11:59 PM
The PHY now works.
There were two issues:
Our pinctrl definitions are now these:
ethernet0_rmii_pins: rmii-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 1, AF11)>, /* ETH1_REF_CLK */
<STM32_PINMUX('B', 12, AF11)>, /* ETH1_TXD0 */
<STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */
<STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */
bias-pull-up;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */
<STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */
<STM32_PINMUX('C', 5, AF11)>, /* ETH1_RXD1 */
<STM32_PINMUX('G', 12, AF11)>; /* ETH1_PHY_INTN */
bias-disable;
};
pins4 {
pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */
};
};
And our ethernet definition:
ðernet0 {
status = "okay";
pinctrl-0 = <ðernet0_rmii_pins>;
pinctrl-names = "default";
phy-mode = "rmii";
phy-handle = <&phy0>;
max-speed = <100>;
snps,reset-delays-us = <0>, <10000>, <1000000>;
snps,reset-gpio = <&gpiob 5 GPIO_ACTIVE_LOW>;
snps,reset-active-low = <1>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@1 {
reg = <0x01>;
};
};
};