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STM32 MCU datasheets: Expected preliminary updates

Imen.D
ST Employee

on ‎2024-06-10 07:00 AM - edited on ‎2024-07-05 04:28 AM by Community manager

Introduction 

This article includes preliminary updates of STM32 MCU datasheets reported since 1st January 2024.  It highlights the current description requiring update and the expected one if available.

The purpose of this article is to deliver any expected updates to our MCU datasheets prior to actual documentation releases. We wish to be transparent with our updates and provide them as fast as possible, to assist you in your design process.
This article is updated on a monthly basis. Once these preliminary updates are manifested in the datasheets, this article is refreshed with new information.
Moving forward, we are also working on providing datasheet releases on a more frequent basis.

IMPORTANT NOTICE - READ CAREFULLY :

  • STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to this article at any time without notice.
  • Information in this article supersedes and replaces information previously supplied in any prior versions of this article.
  • The following table gives a quick reference to the preliminary documentation updates which may be changed or improved without notice. 
  • This article will be reviewed on a monthly basis and applied updates  will be removed from the table.
  • The hyperlinks under "Doc Reference - Revision" provides a direct link to the specific document page where the description is located.

Summary of documentation updates: "STM32 MCU datasheets"

 

Function

Series (Lines) / 
Doc Reference Revision

Update Location

Current Description / 
Expected Description

Date of added update

Pinouts, pin description and alternate functions

STM32H503xx

DS14053 Rev 3

(Sep 2023)

“Table 10. STM32H503xx pin/ball definition” and in all alternate function tables

Current:

In Alternate functions columns:

- USARTx_RTS

- LPUART1_RTS

Expected:

Replace by:

- USARTx_RTS/USARTx_DE

- LPUART1_RTS/LPUART1_DE

Mar 2024

STM32G0B0KE/

CE/RE/VE

DS13565 Rev 2

(Feb 2021)

Table 10. Terms and symbols used in Table 11

Expected:   

-  Add _c, _d and _u symbols for I/O structure

ImenD_0-1720170160979.png

Jun 2024

STM32G0B0KE/

CE/RE/VE

DS13565 Rev 2

(Feb 2021)

Table 11. Pin assignment and description

Current:

The footnote (1):

1.    PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs must not be used as current sources (for example to drive a LED).

Expected:

Update the footnote (1):

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only provides a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs can be used as current sinks but not as current sources.

Jun 2024

Expected:

Add this note and mark the pins mentioned here with a note marker stating this:

- Upon reset, a pull-down resistor might be present on PA8, PB15, PD0, or PD2 depending on voltage level on PA9, PA10, PD1, and PD3, respectively. In order to disable this resistor, strobe the UCPDx_STROBE bits in SYSCFG_CFGR1 register during start-up sequence.

Jun 2024

Current:

The footnote (4) in Table 11. Pin assignment and description:

4.  USB-related alternate or additional functions do not apply to 32-pin package.

Expected:

Remove this note.

Jun 2024

 

STM32WL5MOC

DS14084 Rev 4

(Feb 2024)

 

Table 4. STM32WL5MOC pin definition

Current:

Pin name for pin 42 is PE12

Expected:

Pin 42 must be PA12 (not PE12)

Jun 2024

STM32WL5MOC

DS14084 Rev 4

(Feb 2024)

 

Current:

The footnote (2) for pin 40 must be used only as I2C2_SCL:

2. It must be used only as I2C2_SCL on STM32WL5MOCH6S

Expected:

The footnote (2) must be used as I2C2_SDA (not I2C2_SCL):

2.    It must be used only as I2C2_SDA on STM32WL5MOCH6S

Jun 2024

STM32H533xx

DS14539 Rev 1

(April 2024)

 

 

STM32H523xx

DS14540 Rev 1

(April 2024)

Table xx. STM32H5XXxx pin/ball definition

 

 

Table xx. Alternate function AF0 to AF7

 

 

Table xx. Alternate function AF8 to AF15

Current:

The following name to update:

- LPUART1_RTS

- USART1_RTS

- USART2_RTS

- USART3_RTS

- UART4_RTS

- UART5_RTS

- USART6_RTS

Expected:

The correct name should be:

- LPUART1_RTS/LPUART1_DE

- USART1_RTS/USART1_DE

- USART2_RTS/USART2_DE

- USART3_RTS/USART3_DE

- UART4_RTS/UART4_DE

- UART5_RTS/UART5_DE

- USART6_RTS/USART6_DE

Jun 2024

STM32H523xx

DS14540 Rev 1

(April 2024)

Figure 11. UFBGA144 ballout

Expected:

Replace M12 by VSS in figure 11

Jun 2024

I/O port characteristics

 

STM32H533xx

DS14539 Rev 1

(April 2024)

 

 

STM32H523xx

DS14540 Rev 1

(April 2024)

Figure 20. VIL/VIH for all I/Os except BOOT0

Current:

ImenD_0-1720178608307.png

 


Expected: 

ImenD_1-1720177208854.png

Jun 2024

GPIO

STM32H503xx

DS14053 Rev 3

(Sep 2023)

Table 2. STM32H503xx features and peripheral counts

Current:

Number of GPIOs on UFQFPN32 package: 24

Expected:

Number of GPIOs on UFQFPN32 should be 26.

Mar 2024

RTC

STM32F405xx STM32F407xx

 DS8626 Rev 9

(Aug 2020)

2.2.18 Real-time clock (RTC), backup SRAM and backup registers

Current:

RTC can be clocked by HSE/128:

“It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128.”

Expected: 

It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 2 to 31.

Apr 2024

STM32F405xx STM32F407xx

 DS8626 Rev 9

(Aug 2020) 

Table 33. LSE oscillator characteristics (fLSE = 32.768 kHz)

Current:

The unit of fosc_IN is Mhz.

Expected: 

The unit of fosc_IN should be Khz.

Apr 2024

 

USART

/

UART

 

 

STM32H503xx

DS14053 Rev 3

(Sept 2023)

Figure 1. STM32H503xx block diagram

Current:

USART1, USART2, USART3:

RX, TX, CK, CTS, RTS as AF

Expected:

USART1, USART2, USART3 :

RX, TX, CK, CTS, RTS_DE as AF.

Apr 2024

STM32H533xx

DS14539 Rev 1

(April 2024)

 

 

STM32H523xx

DS14540 Rev 1

(April 2024)

Figure 1. STM32H5XXxx block diagram

Current:

ImenD_2-1720177424958.png

 


Expected:

For USAR1, USART2, USART3, UART4, UART5, USART6:

Update RTS by RTS_DE

Jun 2024

SPI

STM32G0B0KE/

CE/RE/VE

DS13565 Rev 2

(Feb 2021)

Table 1. Features and peripheral counts

Current:

Peripheral counts for SPI [I2S]: 3

Expected:

Peripheral counts for SPI [I2S]: 3 + 6 extra through USARTs

Jun 2024

 

Power Control (PWR)

STM32G0B0KE/

CE/RE/VE

DS13565 Rev 2

(Feb 2021)

Figure 2. Power supply overview

Current:

ImenD_5-1720170160996.png

Expected:

ImenD_6-1720170161001.png

 

 

Jun 2024

 

STM32G0B0KE/

CE/RE/VE

DS13565 Rev 2

(Feb 2021)

Figure 1. Block diagram

Current:

- With PVD

ImenD_7-1720170161003.png

 Expected:

- Remove PVD

ImenD_8-1720170161006.png

Jun 2024

STM32G0B0KE/

CE/RE/VE

DS13565 Rev 2

(Feb 2021)

Figure 9. Power supply scheme

Current:

ImenD_9-1720170161009.png

Expected:

Add VDD and VSS pins, rework decoupling on external VDD net and add a note for VREF+.

ImenD_10-1720170161015.png

Jun 2024

 

STM32G0B0KE/

CE/RE/VE

DS13565 Rev 2

(Feb 2021)

 

Current:

ImenD_11-1720170161017.png

Expected:

ImenD_12-1720170161018.png

Jun 2024

 

STM32G0B0KE/

CE/RE/VE

DS13565 Rev 2

(Feb 2021)

Table 21. Current characteristics

Current:

- The rating: “Current into VDD/VDDA power pin (source)”

Expected:

- Update the rating in the Table 21. Current characteristics to:

“Current into VDD/VDDA and VDD power pins (source)”

Jun 2024

 

TAMPER

STM32H742xI
STM32H742xG STM32H743xI
STM32H743xG

DS12110 Rev 10

(Mar 2023)

Table 2. STM32H742xI/G and STM32H743xI/G features and peripheral counts

Current:

The wakeup pins and tamp pins of STM32H743AI are inverted.

  • Tamper pins : 5     
  • Wakeup pins : 2

Expected : 

Replace by :

  • Tamper pins : 2
  • Wakeup pins : 5

Apr 2024

Operating conditions

STM32H742xI
STM32H742xG STM32H743xI
STM32H743xG

DS12110 Rev 10

(Mar 2023)

Table "General operating conditions" located in sections:

-       Electrical characteristics (rev Y)

-       Electrical characteristics (rev V) sections

Current:

ImenD_14-1720170161023.png

Expected: 

Remove "Ambient temperature for the suffix 3 version" line.

Apr 2024

STM32G031x4

/x6/x8

DS12992 Rev 3

(Oct 2021)

Table. Current consumption in Standby mode

Current:

ULPEN = 0

 

Expected: 

Replace the ULPEN = 0 by ENB_ULP=0.

May 2024

STM32G0C1xC

/xE

DS13564 Rev 4

(Dec 2022)

STM32G041x6

/x8

DS12993 Rev 3

(Oct 2021)

STM32G071x8

/xB

DS12232 Rev 4

(Sep 2021)

STM32G051x6

/x8

DS13303 Rev 3

(Nov 2021)

STM32G061x6

/x8

 DS13513 Rev 3

(Nov 2021)

STM32G081xB

DS12231 Rev 4

(Sep 2021)

STM32G0B0KE/

CE/RE/VE

DS13565 Rev 2

(Feb 2021)

Table 30. Current consumption in Stop 1 mode

Current:

ImenD_3-1720177503071.png

 


Expected:

ImenD_4-1720177572950.png

Jun 2024

 

STM32U083xC

DS14463 Rev 2

(Mar 2024)

 

 

(Applicable for STM32U073xx

DS14548 Rev 2

 (Mar 2024)

Table 40. Current consumption in Stop 2 mode

Current:

For “LCD disabled” condition:

- EN_ULP = 0

- EN_ULP = 1

Expected:

For “LCD disabled” condition:

- EN_ULP = 1

- EN_ULP = 0

Jun 2024

Table 41. Current consumption in Standby mode

Current:

For “No independent watchdog” condition:

- EN_ULP = 0

- EN_ULP = 1

Expected:

For “No independent watchdog” condition:

- EN_ULP = 1

- EN_ULP = 0

Jun 2024

Table 42. Current consumption in Shutdown mode

Expected:

-       Remove in Conditions column: EN_ULP = 0

Jun 2024

STM32H533xx

DS14539 Rev 1

(April 2024)

 

 

STM32H523xx

DS14540 Rev 1

(April 2024)

Table 21. Maximum allowed clock frequencies

Current:

Symbol: "fadc_ker_ck "
Expected: 

Replace by "fadc_ker_ck_input"

Jun 2024

STM32H533xx

DS14539 Rev 1

(April 2024)

Table 20. General operating conditions

Current:

See Table 137 for appropriate thermal resistance and package.

Expected:

See Table 130 for appropriate thermal resistance and package.

Jun 2024

STM32H523xx

DS14540 Rev 1

(April 2024)

Table 19. General operating conditions

Current:

See Table 137 for appropriate thermal resistance and package.

Expected:

See Table 129 for appropriate thermal resistance and package.

Jun 2024

FMC

STM32H533xx

 DS14539 Rev 1

(Apr 2024)

 

 

STM32H523xx

DS14540 Rev 1

(April 2024)

FMC characteristics section

Current:

Missing Figure “Asynchronous multiplexed PSRAM/NOR write waveforms”

Expected: 

Add this figure.

ImenD_5-1720177963304.png

Jun 2024

 

ADC

 

 

 

 

STM32H503xx

DS14053 Rev 3

(Sep 2023)

"12-bit ADC characteristics" section

Current:

"Unless otherwise specified, the parameters given in Table xx are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table yy"

Expected:

Replace "fPCLK2 frequency" by "fHCLK frequency" from the first paragraph in the "12-bit ADC characteristics" section.

Mar 2024

STM32H742xI
STM32H742xG STM32H743xI
STM32H743xG

DS12110 Rev 10

(Mar 2023)

"16-bit ADC characteristics" sub sections located in sections:

-       Electrical characteristics (rev Y)

-       Electrical characteristics (rev V) sections

Current:

"Unless otherwise specified, the parameters given in Table xx are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table yy: General operating conditions".

Expected:

Replace "fPCLK2 frequency" by "fHCLK frequency"from the first paragraph.

Mar 2024

STM32H753xI

DS12117 Rev 9

(Mar 2023)

Mar 2024

STM32H750VB STM32H750ZB STM32H750IB STM32H750XB

DS12556 Rev7

(Mar 2023)

Mar 2024

STM32H735xG

DS13312 Rev 4

(Nov 2023)

Mar 2024

STM32H735xG 

DS13312 Rev 4

(Nov 2023)

Table 89. 12-bit ADC accuracy

Current:

ImenD_6-1720178030946.png

 


Expected:

EG Typical = +/-2 LSBs

EG Max = +/-5 LSBs

May 2024

STM32H742xI
STM32H742xG STM32H743xI
STM32H743xG

 DS12110 Rev 10

(Mar 2023)

Figure 1. STM32H742xI/G block diagram

 

 

Figure 2. STM32H743xI/G block diagram

Current:

In Figure 1. STM32H742xI/G block diagram:

1- Up to 20 analog inputs common to ADC1 & 2.

2- Up to 17 analog inputs common to ADC1 and 2

Expected: 

To replace by:

1-    Up to 20 analog inputs

 Most are common to ADC1 & 2

2-    Up to 17 analog inputs

Some common to ADC1 and 2

Apr 2024

STM32H747xI
STM32H747xG 

DS12930 Rev 2

(Mar 2023)

Figure 1. STM32H747xI/G block diagram

Apr 2024

Memory

STM32H573xx

DS14121 Rev 3

(May 2024)

Table 52 "Flash memory programming"

Current:

ImenD_7-1720178064185.png

Expected:

 

ImenD_8-1720178250214.png

Mar 2024

STM32H562xx and STM32H563xx

 DS14258 Rev 3

(May 2024)

Table 51 "Flash memory programming"

Current:

ImenD_22-1720170161046.png

Expected:

ImenD_23-1720170161048.png

Mar 2024

STM32H523xx

DS14540 Rev 1

(April 2024)

 

 

STM32H533xx

DS14539 Rev 1

(April 2024)

Table 49. Flash memory programming

Current :

ImenD_24-1720170161051.png

Expected :

ImenD_25-1720170161054.png

Jun 2024

STM32U575xx

DS13737 Rev 9

(Feb 2024)

3.4 Embedded flash memory

Current :

Each bank contains 128 pages of 8 Kbytes.

Expected:

For 2-MByte devices: each bank contains 128 pages of 8 KBytes.

For 1-MByte devices: each bank contains 64 pages of 8 KBytes

Jun 2024

 

STM32H523xx

DS14540 Rev 1

(April 2024)

 

 

STM32H533xx

DS14539 Rev 1

(Apr 2024)

Table . Dynamic characteristics: eMMC characteristics, VDD = 1.71 to 1.9 V

Current:

- The max value for Output valid time HS: 7/5

- Footnote (3). When using PB13 and PB14

Expected:

- For Output valid time HS, replace the max value '7/5' by 7/75'

- Replace the footnote (3): " When using PB13 & PB14" by "When using PB13"

Jun 2024

SDMMC

STM32H523xx

DS14540 Rev 1

(April 2024)

 

 

STM32H533xx

DS14539 Rev 1

(April 2024)

Table . SDMMC features

Current:

ImenD_26-1720170161056.png

Expected:

Remove the SDMMC2 column, since the SDMMC2 is not available on STM32H523/533 devices

Jun 2024

STM32H523xx

DS14540 Rev 1

(April 2024)

 

 

STM32H533xx

DS14539 Rev 1

(April 2024)

Table . Dynamic characteristics: SD/MMC characteristics, VDD = 2.7 to 3.6 V

Current:

Footnote: 3. When using PB13 & PB14

Expected:

Replace the footnote 3 " When using PB13 & PB14" by "When using PB13"

Jun 2024

USB

STM32F373xx

D022691 Rev7

(Jun 2016)

Table 12 Alternate functions for port PA.

Current:

Missing USB mapped on PA11-PA12 as AF14 

ImenD_27-1720170161057.png

Expected:

Add USB mapped on PA11-PA12 as AF14.

Apr 2024

STM32G0B0KE/

CE/RE/VE

DS13565 Rev 2

(Feb 2021)

Table 1. Features and peripheral counts

Current:

ImenD_10-1720178390621.png

 


Expected:

Remove “None” for USB from Table 1. Features and peripheral counts.

Jun 2024

 

STM32G0B0KE/

CE/RE/VE

DS13565 Rev 2

(Feb 2021)

3.20 Universal serial bus full-speed host/device interface (USB)

Current:

Note: The embedded USB controller cannot be used on STM32G0B0KE as this device does not provide an HSE oscillator input

Expected:

Note: On STM32G0B0KE device, only HSE external source clock is available.

Jun 2024

 

Package information

STM32F405xx STM32F407xx

DS8626 Rev 9

(Aug 2020)

Table 96. UFBGA176+2 recommended PCB design rules (0.65 mm pitch BGA)

Current:

Table name: UFBGA176+2 recommended PCB design rules (0.65 mm pitch BGA)

Expected:

Table name:

UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA)

Mar 2024
Version history
Last update:
‎2024-07-05 04:28 AM
Updated by:
Community manager
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