The SPI data length is set to 8 bits, but the receive data buffer is 16 bits

[MQi.2]

In STM32WLE5JC MCU, the SPI data length is set to 8 bits, and the corresponding receiving FIFO is also set to 8 bits, but the final receiving and sending data is 16 bits.

1. SPI-CR2 registers during transmission are as follows:

It can be seen from the figure that CR2 is 0x1708, the threshold of FIFO is set to 8 bits, but the data length of DR is 16 bits: 0x0130

2. the CR2 register in 2.STM32WL is described as follows:

[Tesla DeLorean]

Ok, but you understand the debugger is invasive, right?

It forcibly reads, in a wide fashion, and changes the internal state of the peripheral.

It doesn't care about the FIFO depth, or data ready. The data in DR is undefined in the empty case.​