STM32WB5MMG 32.774 kHz clock compensation

[XaviF]

Hi all,

We are using a STM32WB5MMG uC in one of our products and we just happened to see in its datasheet that the secondary crystal frequency is 32.774 kHz, instead of the common 32.768 kHz, is that right?

We are using the internal RTC clocked by the LSE to keep real time in the device and thus we would like to have the least amount of drift, within the crystal manufacturing tolerance.

If that is the case, then I understand a soft calibration of the RTC is needed to account for the +183 ppm with respect to the 32.768 kHz, correct?

By the way, our project is based on the SBSFU+SecureBin+BLE OTA demo project. Is it possible that these already compensate for that?

Thank you all

[STTwo-32 · Accepted solution]

Hello @XaviF 

The nominal frequency of the LSE for the STM32WBxx is 32.768kHz but in the STM32WB5MMG, this frequency is shifted to 32.774kHz (+183ppm). So, in all the application that used the LSE as clock reference (RTC, BLE, …), this shift of the frequency must be considered in the software development.

Best Regards.

STTwo-32

[XaviF]

Hello, thank you for your response.

It looks like this frequence difference can also be compensated using the SYNCH_PRESCALER and ASYNCH_PRESCALER.

Regards