I have designed a board with a STM32H573 and a KSZ8081RNACA PHY. As soon as I enable ETH clocks the ETH_DMAMR:SWR bit gets set.
Verified:
1. The 50 MHz clock from the PHY is present and stable (oscilloscope) at PA1
2. GPIO PA1 is configured for AF11, NOPUPD, SPEED100 as well as all other RMII pins PA2; PA5, PA7, PB12, PB15,PC1,PC4 and PC5
3. HCLK is stable 250MHz
4. Tried forced ETH reset before and after clock enable.
5. Tried to add delays after clock enable
6. Tried to enable ETH clocks one by one or together
7. MDIO is working and all ETH registers are writable
8. I can see traffic on RXD0 (oscilloscope)
If I ignore the set SWR bit I can continue but I never get a ETH interrupt.
I am out of ideas and did not find anything in the errata about it. On a STM32H753 I used for another project a compensation cell bit needed to be set but I dont find this for the STM32H573.
