STM32H573V ETH_DMAMR.SWR stuck

[DirkH]

I have designed a board with a STM32H573 and a KSZ8081RNACA PHY. As soon as I enable ETH clocks the ETH_DMAMR:SWR bit gets set.

Verified:

1. The 50 MHz clock from the PHY is present and stable (oscilloscope) at PA1

2. GPIO PA1 is configured for AF11, NOPUPD, SPEED100 as well as all other RMII pins PA2; PA5, PA7, PB12, PB15,PC1,PC4 and PC5

3. HCLK is stable 250MHz

4. Tried forced ETH reset before and after clock enable.

5. Tried to add delays after clock enable

6. Tried to enable ETH clocks one by one or together

7. MDIO is working and all ETH registers are writable

8. I can see traffic on RXD0 (oscilloscope)

If I ignore the set SWR bit I can continue but I never get a ETH interrupt.

I am out of ideas and did not find anything in the errata about it. On a STM32H753 I used for another project a compensation cell bit needed to be set but I dont find this for the STM32H573.

[DirkH · Accepted solution]

Solved stuck SWR bit. Needed to select RMII during cpu initialisation:

RCC->APB3ENR |= RCC_APB3ENR_SBSEN;
while(!(RCC->APB3ENR & RCC_APB3ENR_SBSEN));

SBS->PMCR |= ( 0x04 << SBS_PMCR_ETH_SEL_PHY_Pos); //Select RMII

// Dummy read to sync with ETH
(void)SBS->PMCR;

[LCE]

Just wanted to post my code for H7, I didn't find the RMII selection...
So thanks for coming back with the solution, please mark your post as solution.

I'm not sure if the peripheral reset makes sense if its clocks are off.

As I just copied it, here it is anyway:

uint8_t EthBaseInit(void)
{
	uint32_t u32TickStart = 0;
	uint32_t u32TempReg = 0;

	/* ETH clock enable */
	__HAL_RCC_ETH1MAC_CLK_ENABLE();
	__HAL_RCC_ETH1TX_CLK_ENABLE();
	__HAL_RCC_ETH1RX_CLK_ENABLE();

	__HAL_RCC_SYSCFG_CLK_ENABLE();

	/* reset Ethernet MAC peripheral */
	DelayX(100);
	__HAL_RCC_ETH1MAC_FORCE_RESET();
	DelayX(100);
	__HAL_RCC_ETH1MAC_RELEASE_RESET();
	DelayX(100);

	/* GPIO init */
	EthGpioInit();

/* set RMII Mode*/
	SYSCFG->PMCR &= ~(uint32_t)SYSCFG_PMCR_EPIS_SEL;
	SYSCFG->PMCR |= (uint32_t)SYSCFG_PMCR_EPIS_SEL_2;
	/* ### IMPORTANT dummy read to sync SYSCFG with ETH */
	(void)SYSCFG->PMCR;

/* SoftWare Reset */
	/* set SWR bit: resets all MAC subsystem internal registers and logic
	 * 	NOTE: the SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
	 *			not available -> check external PHY or IO configuration
	 */
	ETH->DMAMR |= ETH_DMAMR_SWR;
	/* wait for software reset to reset... */
	u32TickStart = HAL_GetTick();
	while( ETH->DMAMR & ETH_DMAMR_SWR )
	{
		/* timeout ? */
		if( (HAL_GetTick() - u32TickStart ) > ETH_TIMEOUT_SWRESET_MS )
		{
			#if DEBUG_ETHNETIF
				uart_printf(SZC_TEXT_ERR "ETH_DMAMR_SWR software reset TO\n\r");
			#endif 	/* DEBUG_ETHNETIF */
			return HAL_TIMEOUT;
		}
	}