STM32WB55 Ram Memory Size

MBuen.1 · ‎2022-07-19

Hello guys, how are you?

I'm investigating some .bss overflows i'm facing and i ended up on some weird question. Linker file for STM32WB generated by CubeMX is as follows:

RAM1 (xrw) : ORIGIN = 0x20000008, LENGTH = 0x2FFF8

RAM_SHARED (xrw) : ORIGIN = 0x20030000, LENGTH = 10K

The sum of this two portions is around ~206K. The STM32WB datasheet says that this MCU has 256K of S-RAM, so.. where are the other 50K of RAM?😂

Remi QUINTIN · ‎2022-07-19

This linker file only defines sections that are accessible to the application running on the M4 core. Remaining parts of the SRAM is used in a secure (protected) way by the wireless stack running on the M0+ core.

Have a look at AN5289 and especially on chapter 4.2 Memory mapping.

Here you'll find a complete description of the split in between the 2 cores and which parts are defined in the linker file.

Note that the RAM_SHARED section is used (and reserved) to exchange data in between the 2 cores.

Some space remains above this section and you can define your own section if you want to locate some of your application data in that memory. But you may face an issue if you size this new section to big as it could conflict with the memory area reserved for the M0+ core.

View solution in original post

Remi QUINTIN · ‎2022-07-19

This linker file only defines sections that are accessible to the application running on the M4 core. Remaining parts of the SRAM is used in a secure (protected) way by the wireless stack running on the M0+ core.

Have a look at AN5289 and especially on chapter 4.2 Memory mapping.

Here you'll find a complete description of the split in between the 2 cores and which parts are defined in the linker file.

Note that the RAM_SHARED section is used (and reserved) to exchange data in between the 2 cores.

Some space remains above this section and you can define your own section if you want to locate some of your application data in that memory. But you may face an issue if you size this new section to big as it could conflict with the memory area reserved for the M0+ core.