Dear all,
I am trying to set-up the internal PLL for running @ 48-MHz.
I can easily set-up the clock tree to achieve frequencies lower than 44-MHz, but when I try 48-MHz, the cpu does not end from the loop that verify that the PLL is OK.
The FLASH is set with 2 WS.
I routed on the MCO the cpu clock and it is correctly set @ 48-MHz
Here is my PLL initialization
...
// For f(ck in) = 16-MHz (HSI16)
// f(out) = f(vco) / R f(out) = 48-MHz, R = 4 ---> f(vco) = 192-MHz
// f(vco) = f(ck in) * (N/M) N/M = 48/4 = 12 ---> N = 48, M = 4
// f(rng) = f(vco) / Q Q = 4 ---> f(rng) = 49.5-MHz
// f(adc) = f(vco) / P P = 4 ---> f(adc) = 49.5-MHz
RCC->PLLCFGR = ((4-1)<<29) // R = 4
| (1<<28) // PLLR enabled
| ((4-1)<<25) // Q = 4
| (1<<24) // PLLQ enabled
| ((4-1)<<17) // P = 4
| (1<<16) // PLLP enabled
| (48<<8) // N = 48
| ((4-1)<<4) // M = 4
| (2<<0); // HSI16 as a PLL source
RCC->CFGR = (0<<28) // MCO (no division)
| (5<<24) // PLLR output
| (0<<11) // APB2 bus @ 41.6/1 = 41.6-MHz
| (0<<8) // APB1 bus @ 41.6/1 = 41.6-MHz
| (0<<4) // HPRE bus @ 41.6-MHz
| (3<<0); // PLL selected as a system clock
// PLLQ for RNG, ..., PCLK (48-MHz) for ...
RCC->CCIPR = (0<<30) // RNG clocked by PLLQ
| (2<<28) // ADC clocked by OPLP
| (0<<22) // LPTIM3 clocked by PCLK
| (0<<20) // LPTIM2 clocked by PCLK
| (0<<18) // LPTIM1 clocked by PCLK
| (0<<16) // I2C3 clocked by PCLK
| (0<<14) // I2C2 clocked by PCLK
| (0<<12) // I2C1 clocked by PCLK
| (0<<10) // LPUART1 clocked by PCLK
| (1<<8) // SPI2 clocked by PLLQ
| (0<<2) // USART2 clocked by PCLK
| (0<<0); // USART1 clocked by PCLK
// Enable PLL
// Waiting for the PLL lock
RCC->CR |= RCC_CR_PLLON;
while ((RCC->CR & RCC_CR_PLLRDY) == 0);
// I can reach this point
RCC->CFGR |= RCC_CFGR_SW;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS);
// ... but I never reach this point for 48-MHz
...
Any glues to solve my problem?
Best regards
Edo
