Putting RAM on QSPI is generally a head-ache. Access efficiencies come from continuous streams, not random access, mixed read/write.
The QSPI NOR Flash memory is cached, I'd recommend using the SOIC16W footprint devices as these are prolific, you can choose to populate one or two. Perhaps accommodate dual-die wiring options.
If using SOIC8 use large land patterns to accommodate parts of differing widths. Watch for annoying mix of ground pad geometries amongst different vendors.
You can't use direct access and memory-mapped concurrently.
You need to code external loaders for unique parts or pin combinations. https://github.com/cturvey/stm32extldr
NOR Flash is optimized for Read, and Erase/Write are SLOW.
A lot of the DISCO/EVAL boards have dual configurations, or single chip, dual die, review schematics.
Benchmark performance, you can try different clocking options, using one chip or both.
