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Looking for STM32 MCU interfacing with DCMI Course

WPong.1
Associate II

I'm looking for STM32 MCU interfacing with DCMI. Can you suggest me where to learn or suggest me online course.

Thank you

1 ACCEPTED SOLUTION

Accepted Solutions
KDJEM.1
ST Employee

Hi @WPong.1​ ,

There is no DCMI course written by STMicroelectronics.

But, I recommended to take a look at:

  • Application note AN5020 Digital camera interface (DCMI) for STM32 MCUs. 
  • DCMI example in STM32Cube package.

Kaouthar

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

View solution in original post

4 REPLIES 4
KDJEM.1
ST Employee

Hi @WPong.1​ ,

There is no DCMI course written by STMicroelectronics.

But, I recommended to take a look at:

  • Application note AN5020 Digital camera interface (DCMI) for STM32 MCUs. 
  • DCMI example in STM32Cube package.

Kaouthar

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

WPong.1
Associate II

Thank you so much. I look at AN5020 but never look at DCMI example in STM32Cube package.

KDJEM.1
ST Employee

HI @WPong.1​ ,

From this page you can choose the suitable STM32Cube MCU package depending on the MCU you work with. 0693W00000SvANGQA3.pngFor example, if you used the STM32F7 MCU you can click on STM32CubeF7/Projects/STM32F769I_EVAL/Examples/DCMI.

So, you can find in this link the DCMI examples with STM32F769I-EVAL board.

When your question is answered, please close this topic by choosing Select as Best. This will help other users find that answer faster.

Kaouthar

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

It's an externally clocked parallel interface, with synchronization signals, clocking at rated independent/disconnected from those than the BUS/CPU operate at.

As I understand it the operation is one typical done with DMA off the FIFOs the interface provides to mitigate clocking disparities. The complexities then revolve around the management of the DMA, ping-pong or double buffering, and the volume of data involved and limits on DMA unit count sizes.

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