2020-01-12 03:25 AM
Hello, I have a stm32f769 discovery board and I run LCD_PicturesFromSDCard example from STM32Cube_FW_F7_V1.15.0.
There is function for drawPixel that save RGB_code to hltdc.LayerCfg[ActiveLayer].FBStartAdress. I understand pixel color is saved to SDRAM via FMC interface. But how it's sended to LCD after that ? There is no configuration for LTDC to read from FMC. Also there is no DMA configuration for that. Maybe DSI interface have configuration for that ? I created project with the same configuration in CubeMX and it's works but I don't know why.
Regards,
Adrian
Solved! Go to Solution.
2020-01-12 09:53 AM
LTDC memory accesses don't go through the regular DMA controller, but you can think of LTDC as having a built-in 2 channel DMA unit. See the system architecture diagram near the beginning of the reference manual, where the LCD controller is shown to have its own bus master access to the system memory bus matrix.
LTDC framebuffer access is configured in the layer configuration registers CFBAR (base address), CFBLR (width), CFBLNR (height) and PFCR (pixel format) for each layer, they determine the sequence of framebuffer read accesses by the built-in DMA. See the register descriptions in the LTDC chapter of the reference manual.
2020-01-12 06:55 AM
> LCD_PicturesFromSDCard example from STM32Cube_FW_F7_V1.15.0
main() of which is in https://github.com/STMicroelectronics/STM32CubeF7/blob/master/Projects/STM32F769I-Discovery/Applications/Display/LCD_PicturesFromSDCard/Src/main.c
Line 107:
> LCD_Config();
That function is then from line 261 on, starting with
> BSP_LCD_Init();
which itself is in https://github.com/STMicroelectronics/STM32CubeF7/blob/master/Drivers/BSP/STM32F769I-Discovery/stm32f769i_discovery_lcd.c
etc.
JW
2020-01-12 09:53 AM
LTDC memory accesses don't go through the regular DMA controller, but you can think of LTDC as having a built-in 2 channel DMA unit. See the system architecture diagram near the beginning of the reference manual, where the LCD controller is shown to have its own bus master access to the system memory bus matrix.
LTDC framebuffer access is configured in the layer configuration registers CFBAR (base address), CFBLR (width), CFBLNR (height) and PFCR (pixel format) for each layer, they determine the sequence of framebuffer read accesses by the built-in DMA. See the register descriptions in the LTDC chapter of the reference manual.
2020-01-12 09:57 AM
Thanks berendi, this was what I looking for.
Regards
Adrian ;)