SPI CRCERR flag not turning on with SPI + DMA

[A_ZA_CH]

I'm struggling to get the SPI CRCERR flag and IRQ to work the way I expect.

I am using an STM32WB55.

The SPI communication in full duplex is working. The master is adding the CRC to the end of the Tx data. On the slave side, the CRC is read in. I can see the RXCRC updating, and I can see it go to 0x00 when the final CRC byte is read, which tells me that the CRC calculation is working. However, I cannot get the CRCERR flag to turn on when I purposefully have a CRC mismatch (using different polynomials on master and slave to trigger a mismatch).

I suspect the issue is related to the DMA transfer sizes. I have read the advice about what length of transfer to use (Tx side = data length without CRC; Rx side = data length with CRC), and I have tried various combinations. I suspect that slave SPI does not know the transfer is done, so it does not do the final comparison and set the error bit.

So, some actual questions:

1. Should I expect the CRCERR flag to work with SPI + DMA on processors like the L4 and WB55?
2. How does the SPI peripheral know when to do the CRC comparison on Rx? Is it based on the length of the DMA Rx transfer request? Or is my mental model of this incorrect?
3. If I want to receive 20 bytes of data + 1 byte of CRC, I understand that I setup the Tx for 20 bytes (and this works, because I see 20 bytes + the 1 byte CRC automatically appended at the end). What should I do on the Rx side? I am asking it for 21 bytes. I have also tried asking for 20 bytes via the DMA, and then "manually" clearing the SPI->DR register of the CRC. Non of these combinations seem to result in the CRCERR flag being set.

Thanks for any input.

[A_ZA_CH · Accepted solution]

Answering my own questions after reading the Ref Manual a few times...

1. Yes, the CRCERR flag does work
2. The length of the CRC data seems to come from the Tx transfer length. When the Tx transfer completes, it does the CRC comparison and checks the flag. At least, it started correctly setting the CRCERR flag on the slave for receiving when I did both an DMA Rx and DMA Tx transfer on the slave (even for slave Rx). I believe the Tx transfer length indicates when to do the CRC comparison and when to set the error flag.
3. To achieve #2 for 20 bytes of data + 1 byte CRC, it seems to be DMA Rx 21 bytes and DMA Tx 20 bytes.