I am using x-cube-sbsfu version 2.4.0 on a custom designed board using the STM32F722. I have ported the single slot code (1_Image) for the STM32F769I-Discovery board to the custom board. I have come across what looks like an error in the sfu_low_level_security.h file. The MPU configuration for the UserApp execution has the access set to bufferable but not cacheable. I believe this will disable the cache, and it also causes memory faults for unaligned memory accesses. Can anybody confirm that this is a mistake in the code?
Here is a snippet for reference (I have changed the region size from 2 MB to 512 kB from the original code):
/**
* MPU configuration for UserApp execution
* =======================================
* Reconfiguration of existing regions (useless during UserApp execution)
* MPU constraint = Region base address should be aligned on Region size
*/
/**
* @brief Region 3 - Enable the execution for active slots in unprivileged mode.
* Read only capability configured
* Inner region inside the Region 2
*/
#define APP_PROTECT_MPU_FLASHEXE_RGNV MPU_REGION_NUMBER3
#define APP_PROTECT_MPU_FLASHEXE_START FLASH_BASE
#define APP_PROTECT_MPU_FLASHEXE_SIZE MPU_REGION_SIZE_512KB
#define APP_PROTECT_MPU_FLASHEXE_SREG 0x00U /*!< All subregions activated */
#define APP_PROTECT_MPU_FLASHEXE_PERM MPU_REGION_PRIV_RO_URO
#define APP_PROTECT_MPU_FLASHEXE_EXECV MPU_INSTRUCTION_ACCESS_ENABLE
#define APP_PROTECT_MPU_FLASHEXE_TEXV MPU_TEX_LEVEL0
// Memory SHOULD be NOT bufferable and cacheable
#define APP_PROTECT_MPU_FLASHEXE_B MPU_ACCESS_BUFFERABLE
#define APP_PROTECT_MPU_FLASHEXE_C MPU_ACCESS_NOT_CACHEABLE
