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Wrong MCU frequency only while debugging

MUrbs.1
Associate

Problem definition:

PLLCLK frequency is different (wrong) in debugging mode only.

Two empty projects were created using CubeMX 6.0.1 and 4.25.1 as a reference.

running exactly the same main.c where only HSE and MCO are enabled outputs different results.

CubeMX 4.25.1 code runs as expected and MCO outputs 216MHz in both regular operation and while debugging

CubeMX 6.0.1 runs incorrectly. Under regular operation the frequency is 216MHz as expected, however in debugging mode the MCO output is 189MHz. It was double checked with timers and comms. Everything is running slower while in debugging mode.

Same thing happens with 12MHz and 25Mhz HSE oscillators.

Test code:

static void ConfigureHSE(void)
{
  RCC->APB1ENR |= RCC_APB1ENR_PWREN;              // Power interface clock enable
 
	while ((RCC->APB1ENR & RCC_APB1ENR_PWREN) != RCC_APB1ENR_PWREN)
	{
	};
 
 
	PWR->CR1 |= PWR_CR1_VOS;                        // Voltage scaling = range 1
 
	while ((PWR->CR1 & PWR_CR1_VOS) != PWR_CR1_VOS)
	{
	};   // Waits until scaling is ready
 
 
	FLASH->ACR = ( FLASH_ACR_PRFTEN |               // Prefetch enable
			FLASH_ACR_LATENCY_7WS);                 // FLASH 4 wait states
 
	RCC->CR &= 0;
	RCC->CR |= RCC_CR_HSEON;                        // Enables HSI clock
 
	while ((RCC->CR & RCC_CR_HSERDY) != RCC_CR_HSERDY)
	{
	};   // Waits until HSI is stable
 
	RCC->PLLCFGR = ( RCC_PLLCFGR_PLLSRC_HSE |       // PLL SRC = HSI
			(12u << RCC_PLLCFGR_PLLM_Pos) |         // PLL_M   =  12
			(432u << RCC_PLLCFGR_PLLN_Pos) |        // PLL_N   =  432
			(0u << RCC_PLLCFGR_PLLP_Pos) |          // PLL_P   =  2
			(2u << RCC_PLLCFGR_PLLQ_Pos));          // PLL_Q   =  2
 
	RCC->CFGR = 0;
	RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
	RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
	RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
 
	RCC->CR |= RCC_CR_PLLON;                        // Enables the PLL
	while (!(RCC->CR & RCC_CR_PLLRDY))
	{
	};   // Waits until PLL is stable
 
	RCC->CFGR &= ~RCC_CFGR_SW;
	RCC->CFGR |= RCC_CFGR_SW_PLL;
	while (!(RCC->CFGR & RCC_CFGR_SWS_PLL))
	{
	};
 
 
  InitializeMCO();
}
/* Displays MCO on PA8 */
static void InitializeMCO(void)
{
	/* Main clock output (MCO): */
	RCC->CFGR &= ~RCC_CFGR_MCO1_Msk;
	RCC->CFGR |= (0x3 << RCC_CFGR_MCO1_Pos);
 
	RCC->AHB1ENR &= ~RCC_AHB1ENR_GPIOAEN;
	RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
 
	GPIOA->MODER &= ~GPIO_MODER_MODER8;
	GPIOA->MODER |= GPIO_MODER_MODER8_1;
 
	GPIOA->OTYPER &= ~GPIO_OTYPER_OT_8;
 
	GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR8;
 
	GPIOA->OSPEEDR &= ~GPIO_OSPEEDER_OSPEEDR8;
	GPIOA->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR8_1;
	GPIOA->AFR[0] &= ~GPIO_AFRL_AFRL0;
}

Thank you in advance for any tips how to fix this

1 REPLY 1

Not sure, the MCO isn't rated at ~200 MHz output, usually needs dividing down.

Would recommend you dump out the RCC registers and compare-n-contrast.

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