With STM32H745 I want to share information between the cores. For this I defined a structure in each core and linked to shared SRAM4 region. I can successfully get data with same core write-read and M4write-M7read. But face problem for M7write-M4read.

[Ashah.2028]

Always get '0' for M7write-M4read.

[Tesla DeLorean]

Check MPU and cache/write thru settings, and make sure to flush the write buffers with a fencing instruction. Think _DSB and DFlash Clean.​

[TDK]

I have this working just fine without any DSB instructions, just defining the variable as volatile which forces the compiler to reload it at every access.

[Tesla DeLorean]

Across two cores, with deferred write buffers, pretty sure you're going to need to get more involved than telling the compiler it's volatile...

[TDK]

I’m reporting my experience. Gnu compiler. Im not guessing at the underlying architecture or what theoretically should/could work.

On this chip, does each core have a deferred write buffer?

[Tesla DeLorean]

They are both independent cores, so definitely more of a situation where things can happen concurrently. Some of the memory is also dual-ported, so perhaps some race hazards to contend with there also.

ST has provided the HSEM to manage inter-core communication/signalling.

In single core multi-threaded the CPU is one unit and provides both a more unified view of memory, and protection against some hazards, along with the sequential granularity stopping some things from "occurring at the same instant" . In multi-core there's a lot more happening, and more balls in the air.

[Ashah.2028]

 By defining as volatile, I got little success. But got satisfactory result after disable of Icache and dcache in M7 i.e. comment out SCB_EnableICache and SCB_EnableDCache functions in main file. ​

Thank you all.