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Ashah.2028 · 2019-12-13

When I use HAL_NVIC_EnableIRQ(64) from CPU1, it interrupts same core (i.e. CPU1 instead of CPU2).

Ashah.2028 · 2019-12-04

Always get '0' for M7write-M4read.

Ashah.2028 · 2019-12-05

By defining as volatile, I got little success. But got satisfactory result after disable of Icache and dcache in M7 i.e. comment out SCB_EnableICache and SCB_EnableDCache functions in main file. Thank you all.

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This is related to Dual Core STM32H745. I want to interrupt from CPU1 to CPU2 (and vise versa). As per reference Manual page 796, NVIC position 64 & 65 can be used. Facing problem to implement the same. Suggest possible cause, please.

With STM32H745 I want to share information between the cores. For this I defined a structure in each core and linked to shared SRAM4 region. I can successfully get data with same core write-read and M4write-M7read. But face problem for M7write-M4read.

Re: With STM32H745 I want to share information between the cores. For this I defined a structure in each core and linked to shared SRAM4 region. I can successfully get data with same core write-read and M4write-M7read. But face problem for M7write-M4read.