Why does uVision (Armcc V5.06) C turn this: SPI1_TX8(addr >> 8); Into this: LSLS r0,r4,#16 LSRS r0,r0,#24 BL SPI1_TX8 Why not just shift 8? By the way addr is uint32_t (unsigned int)

[Tesla DeLorean]

Please try and keep the summary and the question separate when posting.

Why? Because one of these values is a uint8_t and the other a uint32_t, the code is ensuring that the value is within the 0-255 range, in a 32-bit register whose high order bits cannot be guaranteed. The shift back and forth clears the high order bits, and is more efficient than applying an AND or BIC type mask.

[KRogo]

Thanks very much for your reply!

I suspected something like that. I'm relatively new to this CPU and also to C on this CPU. On the CPU's I have worked with extensively, I've coded mainly in assembly.

In those cases, I could always use a SINGLE 32-bit Shift and then use the associated 8-bit LSB register of the register set (in the call to SPI1_TX8 for instance.)

So are you saying it can't be done on this (machine instruction) architecture? or is it a C compiler artifact?

Thanks again!