cancel
Showing results for 
Search instead for 
Did you mean: 

Why does NUCLEO-144 H723ZG measure period time with almost 1Hz error?

Louie88
Associate III

A 720mV RMS sine wave, biased to +1.25V is connected to the PB2 pin. PB2 is the COMP1 positive input. The COMP1 negative input is connected to the internal reference voltage (+1.22V) The output of the comparator is connected to PA0 which is the input capture channel 1 input of TIM2 (32-bit) timer. The TIM2 runs from 275MHz clock and it is started in input capture channel1 with interrupt mode. It works, but it measures 119.3Hz instead of 120Hz. 

I had to set the comparator mode to COMP_POWERMODE_MEDIUMSPEED because with the COMP_POWERMODE_HIGHSPEED I got bouncing signal (spikes, glitches) at the rising/falling edges of the comparator output. The max hysteresis is used.

The error is not large and consequent about 0.6 – 0.7Hz less: The standard deviation also large: 0.07Hz, is should be 0.002Hz.

Maybe the NUCLEO-114 runs from an RC oscillator, not crystal?

As far as I understand the CPU is clocked from HSE clock. It is MCO of STLINK-V3E which is 8MHz. Is this an RC oscillator or crystal? The other acceptable option would be the X3 25MHz crystal, but unfortunately it is not assembled...

Thanks,

Louis

11 REPLIES 11
Peter BENSCH
ST Employee

Typically, the NUCLEO-144 are clocked by the ST-LINK's MCO, with the 8MHz coming from its HSE, which is using an 8MHz crystal.

Do you measure the period, i.e. not the pulse width?

Regards

/Peter

In order to give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
LCE
Principal

The 8 MHz HSE from the STLINK-V3E is from a quarz via the STLINK's STM32, and usually / on my boards not too bad.

The noise comes probably from the combination of low frequency / not so steep flank input signal and the comparator noise.

Concerning the inaccuracy:

  • check your clock source HSI / HSE
  • check your input signal, is it really 120 Hz?
  • check the datasheets concerning the comparator / hysteresis / other stuff
  • check your timer settings and algorithm (maybe forgot to add or subtract 1 somewhere?)

Watch the frequency output by the V3, it is selectable as 25/3, ie 8.33 MHz or from the HSI. Bit of a mess.​

Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..

Hi Peter,

Thanks for the answer!

Because my signal is biased to +1.25V and the comparator compares at +1.2 the the positive comparator output is shorter than the negative one. On scope this is 4.8us and 5.2us @100Hz. Therefore I measure the time between two rising edges (period).

Louis

Louie88
Associate III

Dear LCE,

Thanks for the ideas.

  • I am using HSE.
  • Yes, it is a digital frequency generator, but I also checked it with DVM in frequency mode.
  • Max hysteresis is used (30mV typical)
  • The TIMER2 runs from full speed clock = 275MHz. I do not need to set any divisor, Except DIVIDE by 1, therefore I could set wrong divider.

Thanks,

Louis

Hi Tesla DeLorean,

I am afraid I do not understand you. What is V3 and how I ca set (and why) the 25/2 = 8.33MHz?

Would you pleas explain a bit more?

Thnaks,

Louis

The firmware upgrade tool should show/provide for options as to the source of the clock. None of them are crystal accurate 8 MHz.

Period/Prescale are N-1 numbers. For timing I'd use the TIM in a maximal mode, ie Period=0xFFFF or 0xFFFFFFFF, as it makes the math easier, and less likely to be wrong.

https://www.st.com/resource/en/release_note/rn0093-firmware-upgrade-for-stlink-stlinkv2-stlinkv21-and-stlinkv3-boards-stmicroelectronics.pdf

On STLINK-V3E boards: – Possibility added to choose the MCO clock output from ST-LINK to target among 3 values. The default value (HSI / 2 = 8 MHz) can be changed through STLinkUpgrade applications to HSE / 3 = 8.33 MHz (for better clock accuracy) or cut off. The operation is reversible. In case of a switch to 8.33 MHz, the target application must be updated accordingly: a factor × (24 / 25) must be applied in the PLL configuration in order to keep the clock tree unchanged behind (for instance, if PLLN = 400, set PLLN = 384). Moreover the HSE_VALUE constant commonly defined into stm32xxx_ hal_conf.h must be changed to value 8333333.

Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..
Michal Dudka
Senior III

Value is about 1% off (typical HSI error value). Also short term deviations are typical for HSI. Looks like you are running from HSI. Double check your clock source. Simply put fraction of your SYSCLK to MCO (PA8/PC9?) and look by scope on HSE input frequency and your MCO output. If they are, you can be sure that you are running from HSE and you can search elsewhere - for example at comparator output.

Michal Dudka
Senior III

correction: *If they are in phase.