cancel
Showing results for 
Search instead for 
Did you mean: 

Why does my STM32L5 peripheral clock keep running in stop 2 mode

Lvan .2
Associate

I am using an STM32L552ZE (it is in fact the nucleo version). After carefully reading the manual and looking at some example code from the STM32 Cube IDE, I came to the conclusion that this code is what I need to enter stop 2 mode with Wait For Event:

PWR->CR1 =                       //
    (PWR->CR1 & (~PWR_CR1_LPMS)) // Clear Low Power Mode Select bits
    | PWR_CR1_LPMS_STOP2         // Select Stop 2 Mode
    ;
 
// Deep sleep
SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
 
// Wait for event
__SEV();
__WFE();
__WFE();

This works very well as the processor indeed stops running. I am also able to wake the processor by sending a byte on the LPUART interface (which is clocked by the LSE).

HOWEVER, now I also configure some (non LP) timers and then the MCU is immediately woken up. Even though the timers are configured using their corresponding APB clock, which supposedly should be disabled in stop 2 mode.

My question now is, how is it possible that an APB clocked peripheral can wake my MCU from stop 2 mode?

1 ACCEPTED SOLUTION

Accepted Solutions
Lvan .2
Associate

I just found out the debugger sets the 'DBG_STOP' and 'DBG_STANDBY' bits in the DBGMCU.CR register, which causes the clocks to keep running. These flags are not cleared on reset, so the system must be power cycled before the stop mode can be properly tested.

Leaving this here for anyone interested.

View solution in original post

1 REPLY 1
Lvan .2
Associate

I just found out the debugger sets the 'DBG_STOP' and 'DBG_STANDBY' bits in the DBGMCU.CR register, which causes the clocks to keep running. These flags are not cleared on reset, so the system must be power cycled before the stop mode can be properly tested.

Leaving this here for anyone interested.