Which internal memory address is memory mapped QUAD SPI mapped to?

[anonymous.8]

Posted on March 11, 2018 at 20:33

Hi, I want to setup my STM32F767 QUAD SPI peripheral to access an external NOR FLASH chip in memory mapped mode.

I can see from the STM32F76xxx reference manual how to set the QUADSPI->CCR register to set the FLASH memory command and frame format to configure it in memory mapped mode. Besides setting the CCR register, is there anything else I need to do, apart from the Timeout counter etc., to setup to operate it in memory mapped mode?

But I have not found anywhere in either the datasheet or the reference manual that defines which internal memory addresses are used to map the QUAD SPI peripheral to when it is operated in the memory mapped mode for reading from the FLASH chip.Does anyone know this?Thanks.

[Tesla DeLorean]

Posted on March 11, 2018 at 23:02

Examples I've seen all decode at 0x90000000

[waclawek.jan]

Posted on March 11, 2018 at 23:49

Clive One wrote:

Examples I've seen all decode at 0x90000000

Indeed.

Might've been mentioned in RM, too...

JW

[Tesla DeLorean]

Posted on March 12, 2018 at 00:26

My copy of RM0410 (Rev 3, Nov 2017, STM32F76xxx and STM32F77xxx) was less than illuminating on the topic. Closest to a mention was 0x90000000-0x9FFFFFFF was Bank 4 Reserved on the FMC

http://www.st.com/en/microcontrollers/stm32f767zi.html

 

http://www.st.com/content/ccc/resource/technical/document/reference_manual/group0/96/8b/0d/ec/16/22/43/71/DM00224583/files/DM00224583.pdf/jcr:content/translations/en.DM00224583.pdf

 

[waclawek.jan]

Posted on March 12, 2018 at 00:30

I didn't find it (directly) in RM either - the screenshot is from the DS...

Jan

[anonymous.8]

Posted on March 12, 2018 at 00:33

Yes I've now found some examples using address 

0x90000000, and even found the following in the stm32f765xx.h device file

♯ define QSPI_BASE 0x90000000U    /*!< Base address of : QSPI memories accessible over AXI */

However, there is no mention of this address in the reference manual RM04010 document.

That manual does have the 'Table 1. STM32F76xxx and STM32F77xxx register boundary addresses', but that table, in that particular document, excludes the QSPI_BASE address. Obviously an omission on ST's part as some other reference manuals for other devices do include it.

But now looking at the datasheet, which usually is not very detailed, again, I do see the above Table 14.So problem, solved.

Thanks folks.

[Tesla DeLorean]

Posted on March 12, 2018 at 00:41

http://www.st.com/content/ccc/resource/technical/document/datasheet/group3/c5/37/9c/1d/a6/09/4e/1a/DM00273119/files/DM00273119.pdf/jcr:content/translations/en.DM00273119.pdf

 

Yes, see it there, well that's just more depressing. Can we get an 'About the documentation' sub-forum?

[Nesrine M_O]

Posted on March 13, 2018 at 17:37

Hi,

Thank you for highlighting this issue

.This is noted and will be fixed in coming release of the reference manual.

-Nesrine-