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When cache is enable DMA not update data

MDeva.1
Associate II

I am working on Nucleo-h745ziq board .I am enable the ADC ch3 and 12 bit resolution ,DMA is enabled and circular mode. I connect the 3v supply to ADC channel. But I doesn't get the updated value when I reset board I get updated value, when I disable the cache i get the updated value .Below are the setup I done. Can you please help me to solve this issue.

uint8_t flag;

__attribute__((section(".buffer"),used)) uint32_t ADCbUFF[1];

void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)

{

flag=1;

}

 MX_GPIO_Init();

 MX_USART3_UART_Init();

 MX_DMA_Init();

 MX_ADC1_Init();

 MX_SPI1_Init();

 /* USER CODE BEGIN 2 */

 HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED);

 HAL_ADC_Start_DMA(&hadc1, (uint32_t*)ADCbUFF, 1);

 /* USER CODE END 2 */

 /* Infinite loop */

 /* USER CODE BEGIN WHILE */

 while (1)

 {

  /* USER CODE END WHILE */

  /* USER CODE BEGIN 3 */

 if(flag==1)

     {

     printf("ADC value=%ld\n\r",ADCbUFF[0]);

     flag=0;

     HAL_Delay(2000);

     }

 }

static void MX_ADC1_Init(void)

{

 /* USER CODE BEGIN ADC1_Init 0 */

 /* USER CODE END ADC1_Init 0 */

 ADC_MultiModeTypeDef multimode = {0};

 /* USER CODE BEGIN ADC1_Init 1 */

 /* USER CODE END ADC1_Init 1 */

 /** Common config

 */

 hadc1.Instance = ADC1;

 hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV2;

 hadc1.Init.Resolution = ADC_RESOLUTION_16B;

 hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;

 hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;

 hadc1.Init.LowPowerAutoWait = DISABLE;

 hadc1.Init.ContinuousConvMode = ENABLE;

 hadc1.Init.NbrOfConversion = 1;

 hadc1.Init.DiscontinuousConvMode = DISABLE;

 hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_CIRCULAR;

 hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;

 hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;

 hadc1.Init.OversamplingMode = ENABLE;

 if (HAL_ADC_Init(&hadc1) != HAL_OK)

 {

  Error_Handler();

 }

 /** Configure the ADC multi-mode

 */

 multimode.Mode = ADC_MODE_INDEPENDENT;

 if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)

 {

  Error_Handler();

 }

 /* USER CODE BEGIN ADC1_Init 2 */

 /* USER CODE END ADC1_Init 2 */

}

void SystemClock_Config(void)

{

 RCC_OscInitTypeDef RCC_OscInitStruct = {0};

 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

 /** Supply configuration update enable

 */

 HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);

 /** Configure the main internal regulator output voltage

 */

 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);

 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}

 /** Macro to configure the PLL clock source

 */

 __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);

 /** Initializes the RCC Oscillators according to the specified parameters

 * in the RCC_OscInitTypeDef structure.

 */

 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;

 RCC_OscInitStruct.HSEState = RCC_HSE_ON;

 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;

 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;

 RCC_OscInitStruct.PLL.PLLM = 1;

 RCC_OscInitStruct.PLL.PLLN = 120;

 RCC_OscInitStruct.PLL.PLLP = 2;

 RCC_OscInitStruct.PLL.PLLQ = 32;

 RCC_OscInitStruct.PLL.PLLR = 2;

 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;

 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;

 RCC_OscInitStruct.PLL.PLLFRACN = 0;

 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)

 {

  Error_Handler();

 }

 /** Initializes the CPU, AHB and APB buses clocks

 */

 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK

               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2

               |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;

 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;

 RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;

 RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;

 RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;

 RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;

 RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;

 RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;

 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)

 {

  Error_Handler();

 }

}

void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)

{

 GPIO_InitTypeDef GPIO_InitStruct = {0};

 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};

 if(hadc->Instance==ADC1)

 {

 /* USER CODE BEGIN ADC1_MspInit 0 */

 /* USER CODE END ADC1_MspInit 0 */

 /** Initializes the peripherals clock

 */

  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC;

  PeriphClkInitStruct.PLL2.PLL2M = 2;

  PeriphClkInitStruct.PLL2.PLL2N = 129;

  PeriphClkInitStruct.PLL2.PLL2P = 18;

  PeriphClkInitStruct.PLL2.PLL2Q = 2;

  PeriphClkInitStruct.PLL2.PLL2R = 2;

  PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2;

  PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;

  PeriphClkInitStruct.PLL2.PLL2FRACN = 0;

  PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;

  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)

  {

   Error_Handler();

  }

  /* Peripheral clock enable */

  __HAL_RCC_ADC12_CLK_ENABLE();

  __HAL_RCC_GPIOA_CLK_ENABLE();

  /**ADC1 GPIO Configuration

  PA6   ------> ADC1_INP3

  */

  GPIO_InitStruct.Pin = GPIO_PIN_6;

  GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;

  GPIO_InitStruct.Pull = GPIO_NOPULL;

  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);

  /* ADC1 DMA Init */

  /* ADC1 Init */

  hdma_adc1.Instance = DMA1_Stream0;

  hdma_adc1.Init.Request = DMA_REQUEST_ADC1;

  hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;

  hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;

  hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;

  hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;

  hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;

  hdma_adc1.Init.Mode = DMA_CIRCULAR;

  hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;

  hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;

  if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)

  {

   Error_Handler();

  }

  __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);

  /* ADC1 interrupt Init */

  HAL_NVIC_SetPriority(ADC_IRQn, 0, 0);

  HAL_NVIC_EnableIRQ(ADC_IRQn);

 /* USER CODE BEGIN ADC1_MspInit 1 */

 /* USER CODE END ADC1_MspInit 1 */

 }

}

1 ACCEPTED SOLUTION

Accepted Solutions
3 REPLIES 3

https://en.wikipedia.org/wiki/Cache_coherence

https://www.youtube.com/watch?v=6JMd-3q8Dnw

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MDeva.1
Associate II

Thank you .Its very helpful .