Hi ST
We saw from STM32F302x6/x8 device errata ES0247 - Rev 8 - February 2019
2.4.4 ADEN bit cannot be set immediately after the ADC calibration is done Description At the end of the ADC calibration, there is an internal reset of ADEN bit 4 ADC clock cycle after the ADCAL bit cleared by hardware. Due to that, if ADEN bit is set within those four ADC clock cycles, it will be reset by the calibration logic and the ADC will stay disabled.
Workaround Adopt one of the following measures:
Continue to set the ADEN bit, until ADRDY bit become '1'.
After ADCAL is cleared, wait for a minimum of four ADC clock cycles before setting the ADEN bit.
The workaround 1 seems conflict with RM (RM0365 Rev 8):
Software is allowed to set ADEN only when all bits of ADCx_CR registers are 0 (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator)
Could you please help clarify :
- Is it ok to use work around 1 ? Any side effect ?
