What's wrong with this WWDG initialization code?

[AVoel.1]

Based on the info in the STM32 reference manual, I would have thought this code to start up the WWDG would work (after processor reset).

// sets up the WWDG with a period of about 1 sec, no lower limit
inline void StartWwdg() {
  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG);
  for (int i=0; i<100; i++) {}       // do we need to wait for the clock enable?
  WWDG->CFR = (3<<7) | (1<<9);       // divide by 2^8, EWI enabled, no lower limit
  WWDG->SR = 0;
  WWDG->CR = (1<<7) | (1<<6) | 14;   // divide by 14, enable wwdg
}

(The pclk frequency is 16 Mhz)

However, after stepping through in the debugger, I immediately lose contact the debugger after stepping over line 7 (presumably because of a reset). I cannot figure out what is wrong with the code. Any help would be welcome.

[waclawek.jan]

Which STM32?

Once you enable a watchdog, you have to refresh it periodically - which you don't do when you single-step in debugger, so it's just normal that it resets after the watchdog expires without being refreshed.

Some STM32 have an option to "freeze" the watchdog while single-stepping, in the DBGMCU freeze registers, see the WWDG and DGB chapters in RM to your STM32.

JW

[AVoel.1]

I know you have to refresh it periodically - that's pretty obvious.

But I think I just figured the problem. The WWDG *can't* be configured with anything other than a super short timeout. I was misreading thing the divisor was 2^8, not 8. Why they designed it this way, now that's a mystery.